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DPS sa FPGA

DPS sa FPGA. Direktna implementacija FIR filtara. Direktni FIR filtar. SOP: PROCESS (a,p) BEGIN FOR I IN 0 TO L-2 LOOP -- Compute the transposed a(I) <= (p(I)(W2-1) & p(I)) + a(I+1); -- filter adds END LOOP;

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DPS sa FPGA

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  1. DPS sa FPGA Direktna implementacija FIR filtara

  2. Direktni FIR filtar SOP: PROCESS (a,p) BEGIN FOR I IN 0 TO L-2 LOOP -- Compute the transposed a(I) <= (p(I)(W2-1) & p(I)) + a(I+1); -- filter adds END LOOP; a(L-1) <= p(L-1)(W2-1) & p(L-1); -- First TAP has y <= a(0); END PROCESS SOP; b[L–1] b[L–2] b[L–3] b[0] Load: PROCESS BEGIN WAIT UNTIL clk = '1'; IF (Load_x = '0') THEN c(L-1) <= c_in; -- ucitavanje koeficijenta FOR I IN L-2 DOWNTO 0 LOOP -- pomeranje koeficijenata c(I) <= c(I+1); END LOOP; ELSE b(L-1) <= x_in; -- ucitavanje ulaza FOR I IN L-2 DOWNTO 0 LOOP -- pomeranje ulaza b(I) <= b(I+1); END LOOP; END IF; END PROCESS Load; p[0] p[L–1] p[L–2] p[L–3] MulGen: FOR I IN 0 TO L-1 GENERATE Muls: lpm_mult -- p(i) = c(L-1-i) * b(i); GENERIC MAP ( LPM_WIDTHA => W1, LPM_WIDTHB => W1, LPM_PIPELINE => Mpipe, LPM_REPRESENTATION => "SIGNED", LPM_WIDTHP => W2, LPM_WIDTHS => W2) PORT MAP ( clock => clk, dataa => b(I), datab => c(L-1-I), result => p(I)); END GENERATE; a[L–2] a[L–3] a[0]

  3. Zauzetost komponente • LE: 163 • MULT: 4 • 216.73MHz

  4. Transponovani FIR filtar Load: PROCESS BEGIN WAIT UNTIL clk = '1'; IF (Load_x = '0') THEN f(L-1) <= f_in; -- preuzimanje koeficijenta FOR I IN L-2 DOWNTO 0 LOOP -- shiftovanje keoficijenata f(I) <= f(I+1); END LOOP; ELSE x <= x_in; -- sample END IF; END PROCESS Load; MulGen: FOR I IN 0 TO L-1 GENERATE Muls: lpm_mult -- Multiply p(i) = c(i) * x; GENERIC MAP ( LPM_WIDTHA => W1, LPM_WIDTHB => W1, LPM_PIPELINE => Mpipe, LPM_REPRESENTATION => "SIGNED", LPM_WIDTHP => W2, LPM_WIDTHS => W2) PORT MAP ( clock => clk, dataa => x, datab => f(I), result => p(I)); END GENERATE; SOP: PROCESS (clk) BEGIN IF clk'event and (clk = '1') THEN FOR I IN 0 TO L-2 LOOP a(I) <= (p(I)(W2-1) & p(I)) + a(I+1); END LOOP; a(L-1) <= p(L-1)(W2-1) & p(L-1); END IF; y <= a(0); END PROCESS SOP; p[L–2] p[L–1] p[L–3] p[0] a[0] a[L–3] a[L–1] a[L–2]

  5. Zauzetost komponente • LE: 184 • MULT: 4 • 216.73MHz

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