Matrix Processor / Backplane Design Details

1. Matrix Processor / Backplane Design Details 26.02.2008 John Jones Princeton University Matt Stettler LANL

2. Aims Of These Slides Try to summarise/clarify details of the system that have not been previously discussed Clarify the connections on the backplane… …and their relationship to the matrix processor Clock system options JTAG options Ethernet usage Signal standards John Jones (john.jones@cern.ch)

3. uTCA Specifications uTCA is an AC-coupled serial system Required by specification Default signal standard for serial links is CML Use of any other standard requires card negotiation with the host Signals must be tristated until host ‘agrees’ to power-up This means we can use, e.g. Ethernet on a link, provided we negotiate the protocol with the host Standard for clocks is LVDS Basic specification allows for 21 serial channels and 3 clocks Specification was amended to provide 20 channels and 4 clocks… …however either is still acceptable John Jones (john.jones@cern.ch)

4. Matrix Processor Switch has 72 bi-directional links: 16 to OptoTX/RX 16 to V5 MGTs 20 to backplane 20 to V5 LVDS IOBs OptoTX 20 Mindspeed 72x72 Backplane 16 OptoRX 16 20 Enet V5-LXT110 uC AC-coupled CML AC-coupled LVDS John Jones (john.jones@cern.ch)

5. Matrix Backplane Design uTCA allows for 3U or 6U implementations In the backplane we take advantage of this to simplify routing Backplane is actually two identical boards Each supports 12 3U full-height cards or 6 6U full-height cards Design is intended to be fully uTCA compliant We can use standard commercial boards as well… Significant difference in the way specifications are supported: Typically routing of links would be handled by a host card (MCH) As we have a switch on the backplane that controls the links, the backplane takes on the full functionality of an MCH There is no need for an MCH slot in this design Dual-redundant power supplies are not included in the current schematic Significantly complicates backplane layout John Jones (john.jones@cern.ch)

6. Matrix (Half-)Backplane – Layout (TTC) Input slot S1 S2 S3 S4 S5 S6 V5 Switch Clk/ Eth Power S12 S11 S10 S9 S8 S7 John Jones (john.jones@cern.ch)

7. Matrix Backplane – Switch connections Backplane switch has 144 bi-directional links: 12x10 (120) to card slots 12 to backplane FPGA 12 to input card slot Control V5-LXT110 Slot 1 12 10 5 10 4 Mindspeed 144x144 Slot 2 5 10 12 (TTC) Input slot Slot 3 John Jones (john.jones@cern.ch)

8. Matrix Backplane – Clock Fan-Out 1 Control V5-LXT110 Slot 1 Local OSC 2 1 1 Fractional-N Synthesis 1 4  2 Fan-out Slot 2 2 1 2 2 (TTC) Input slot Slot 3 1 John Jones (john.jones@cern.ch)

9. Comments Use MGTs for high-bandwidth data Isosynchronous but the fastest transport mode Neighbouring slots have 5 links between each of them Can be used for ‘geometric’ processing (e.g. nearest-neighbour) Use Manchester-encoded LVDS for synchronous signal distribution Up to 500MHz throughput in a Virtex 5 Routed through switch – protocol agnostic, works from DC to 4GHz JTAG chain in crate is controlled by FPGA/uController on backplane Automatically routed through active cards Can be reconfigured by changing FPGA settings over Ethernet Accessible from connector on (TTC) input card Backplane FPGA is isolated from chain (separate connector on backplane) If additional clocks needed, use the LVDS signals Can be routed to other cards using switch Cannot be used for MGTs – no obvious reason to have more than two MGT clocks John Jones (john.jones@cern.ch)