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Processor Design

Content. GPR processor non pipeline implementationGPR processor pipeline implementationPerformance Issues in pipeline. Pipeline. Pipelining is an implementation technique whereby multiple instructions are overlapped in executionThe goal of the pipeline is to reduce the execution time for a s

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Processor Design

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    1. Processor Design CT213 – Computing Systems Organization

    2. Content GPR processor – non pipeline implementation GPR processor – pipeline implementation Performance Issues in pipeline

    3. Pipeline Pipelining is an implementation technique whereby multiple instructions are overlapped in execution The goal of the pipeline is to reduce the execution time for a set of instructions Today, pipelining is the key implementation technique for modern processors Each stage in the pipeline completes a part of the instruction Throughput is determined by how often an instruction exits the pipeline (gets completed)

    4. GPR Example processor (1) Consider a simple GPR architecture 32 GPR registers, R0 to R31 Value of R0 is always 0 Data types: 8 bit bytes, 16 bit half words and 32 bit words (integer data) Operations work on 32 bit integers 8 bit and 16 bit operands are loaded into the 32 bit registers with sign bit duplicated Addressing modes: Immediate (16 bit field) Displacement mode (contents of register added to 16 bit address field)

    5. GPR Example Processor (2) Examples of I Instructions LW R2, 50 (R3) – Regs[R2] <- Mem{50 + Regs[R3]} LW R2, 50 (R0) – Regs[R2] <- Mem{50 + 0} SW R3, 500 (R4) – Mem{500+Regs[R4]}<-Regs[R3] BNEZ R4, name – if (Regs[R4]){PC<-name} JR R3 – PC<- Regs[R3] (jump register) JALR R2 – Regs[R31] <-PC+4; PC<-Regs[R2] (jump and link register)

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