Putting the Software Radio on a Low-Calorie Diet Prabal Dutta, Ye-Sheng Kuo, Akos Ledeczi, Thomas Schmid, Peter Volgyesi

1. Putting the Software Radio on a Low-Calorie Diet Prabal Dutta, Ye-Sheng Kuo, Akos Ledeczi, Thomas Schmid, Peter Volgyesi HotNets’10 – Monterey, CA – October 20, 2010

2. Software radios have enabled novel directions in wireless research

3. Mobile and low-power wireless research has not benefitted as much from software radios USRP Mote • Three SDR scaling challenges • Power (Active and Sleep) • A: USRP (10 W) vs Mote (60 mW) • S: USRP (10 W?) vs Mote (20 W) • Cost • USRP ($850) vs Mote ($65) • WARP cost >> USRP cost • Size • USRP (36 in2) vs Mote (1 in2) • WARP (64 in2) vs Mote (1 in2)

4. Imagine if we could build a small, inexpensive, and low-power software radio • Software radios that you could • Hold in the palm of your hand • Embed in the physical world • Deploy at very large scale • Operate from solar power • Hand out for student labs • Software radios that would enable • Mobile networking research • Application-driven research • Large-scale, in situ evaluations • Energy-adaptive communications • Hands-on learning

5. Addressing the size, power, and cost challenges will enable more natural deployment experiences

6. Outline • Introduction • Scaling Challenges • Technology Enablers • Architectural Sketch • Research Challenges

7. Challenge #1: Power • Low-power systems duty cycle • Attempt to achieve power proportional operation • Architectures support power control • High CPU and radio power draws • Radio turned off or in standby • CPU halted and put to sleep • SDRs cannot duty cycle • Fail to achieve power proportional operation • Architectures do not support it • Processor does not support sleep • SRAM-based FPGA cannot sleep • Radio power controls not exposed

8. Challenge #1: Power(or, why SRAM FPGAs are not power-proportional) • High in-rush current • High static power • Approximately 10x transistors needed • Increases with smaller transistors • Increases with lower Vth • High configuration current (and time) • Not amenable to efficient duty cycling

9. Challenge #2: Size(or, why modularity is expensive) • Conventional SDRs • General-purpose • Highly reconfigurable • Modular platforms • Large size • Reconfigurable Motes • Application-specific • Modestly reconfigurable • Not modular • Small size • Examples • Waldo Mote • Bridge Monitor Waldo Mote. Src: S. Lanszisera Bridge Monitor. Src: P. Volgyesi

10. Challenge #3: Cost(or, why discrete components drive up costs) • XC4VFX100-10FF1517C FPGA • 94,896 logic cells • $2400 • Radio board • MAX2829 • Power Amp • Ant Switch • SMA I/F • AD9777 • AD9248 • AD9200 http://warp.rice.edu/trac/wiki/HardwarePlatform

11. Summary of the scaling challenges • Power • SRAM FPGAs have high static power and cannot duty cycle • SDR architectures do not support power controls • Size • Modular designs are large and 3-dimensional • Discrete chips for RF and baseband pathways take up space • Cost • Ultra high-performance FPGAs are expensive • Discrete chips for RF and baseband pathways is costly

12. Outline • Introduction • Scaling Challenges • Technology Enablers • Architectural Sketch • Research Challenges

13. Emerging mixed-signal FPGAs (e.g. Actel SmartFusion) • Integrates • FPGA (200K/500K gates) • Hard CPU (ARM Cortex-M3) • Analog Compute Engine (ACE) • FPGA • Flash-based • Low-power • Logic tiles + SRAM blocks • CPU • 100 MHz+ operation • 64K SRAM / 256K Flash • FPGA memory-mapped on AHB • ACE • 600 ksps ADC/DAC • Fast comparators • Simple DSP operations http://www.actel.com

14. CPU and FPGA compute fabrics interfaced via AHB CPU FPGA Source: ActelSmartFusion MSS User Guide

15. Flash-based FPGA can be duty cycled • Low in-rush current • Low static power (W) • No configuration current • No configuration delay • Amenable to duty cycling • “FlashFreeze” mode • Clock domains suspended • High-impedance I/O • Memory contents preserved • Limitations • Slow max speed (10-40 MHz) • Lower gate count (130 nm node) • Long reprogramming time (flash erase/write) • Limited number of programming cycles (~1000)

16. Highly-integrated RF transceivers • Small layout size • Approx 150 mm2 • Including externals • Low-power • Active: ~200-900 mW • Sleep: ~30 W • High integration • RF transceiver • Integrated PA • Integrated RX/TX SW • Integrated diversity SW • ADCs/DACs • Integrated in FPGA • (at least slow ones)

17. Outline • Introduction • Scaling Challenges • Technology Enablers • Architectural Sketch • Research Challenges

18. Architectural sketch of a lean SDR platform • Mixed-signal FPGA • Flash-based matrix + PLL • ARM Cortex CPU (M1 or M3) • ADC/DAC/Analog Comparator • 2.4 GHz Radio • RF-to-baseband • Osc, Dig Frq Synth • PA, RX/TX Switch • Timebase • 32 kHz TCXO + DCO + VHT • Power • DC/DC converters • Energy metering • Optional • 40 Msps ADC / 40 MHz DAC

19. Addressing the scaling challenges • Power • SRAM FPGAs have high static power  Use Flash-based FPGAs • SDRs do not support power controls  Support Power Mgmt • Size • Modular designs are large  De-modularize the design • Discrete chips take up space  Leverage IC integration • Cost • High-end FPGAs are expensive  Remove, complement with CPU • Discrete chips are costly  Leverage integration, PCB Ant, …

20. A few other odds and ends… • Power-proportional timer system • Offers virtual high-resolution time • Balances fast-timer resolution (xx:34) • …with slow-timer power draw (12:xx) • Provides resolution on demand • Fast radio startup • Accelerates sleep  active transition • Uses crystal to train ring oscillator • Uses ring oscillator to kickstart crystal • Balances high-Q and fast radio startup • Regulator-integrated energy meter • Supports application-level power profiling • Counts switching cycles of regulator • Transfers fixed energy quanta per cycle

21. Back-of-the-envelope evaluation Desc Mfg Part Size Cost Power (mW) FPGA Actel A2F200M3F 17x17 mm $40 TBD* Radio Maxim MAX2830 7x7 mm $4 186/0.030 OSC Maxim DS32kHz 11x11 mm $4 0.005/na PCB 4PCB 4-layer PCB 38x63 mm $5 na Power TI Various 25x25 mm $5 20% overhead ADC ADI AD9288 9x9 mm $6 156/6 DAC Maxim MAX5189 6x10 mm $5 7/1 Misc Various Various Various$31n/a ~4 x 6 cm ~$100 ~350/10 * Actel IGLOO active power ~ 10’s mW and standby power ~10 W. * Actel SmartFusion power to be characterized.

22. Outline • Introduction • Scaling Challenges • Technology Enablers • Architectural Sketch • Research Challenges

23. Time multiplex algorithms on the CPU orparallelize algorithms on the FPGA fabric? FPGA • Verilog/VHDL RTLs • Parallel • Fast to run • Hard to write • Great power-efficiency • Gate-limited • Use soft CPU core? • CPU • Assembly/C/C++ • Sequential • Slow to run • Easy to write • Poor power-efficiency • Memory-limited • Use hard CPU core

24. How should we reuse existing SDR libraries? • Lots of SDR & soft router software • Better to not reinvent the wheel • How can these libraries be wrapped? • Implications on computation model? Click http://gnuradio.org/redmine/repositories/browse/gnuradio/gnuradio-core/src/lib

25. Let chaos reign… then rein in the chaos • Many basic architectural questions • How much low-level detail should be exposed to applications? • How to balance component library flexibly and reuse? • How should computations be scheduled? • But many questions don’t need immediate answers • Allow exploration of the design space • Allow competing software architectures • Eventually converge on known good design points

26. Outline • Introduction • Scaling Challenges • Technology Enablers • Architectural Sketch • Research Challenges

27. This work is about finding a middle ground USRP SDR Mote

28. Questions? Comments? Discussion?