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Computer Architecture

Computer Architecture. Storage Systems Prof. Jerry Breecher. Chapter Overview. 6.1 Introduction 6.2 Types of Storage Devices 6.3 Busses - Connecting IO Devices to CPU/Memory. Interrupts etc. How is data transferred. 6.5 Reliability, Availability and RAID.

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Computer Architecture

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  1. Computer Architecture Storage Systems Prof. Jerry Breecher

  2. Chapter Overview 6.1 Introduction 6.2 Types of Storage Devices 6.3 Busses - Connecting IO Devices to CPU/Memory. Interrupts etc. How is data transferred. 6.5 Reliability, Availability and RAID Chap. 6 - Storage

  3. The Big Picture: Where are We Now? Introduction 6.1 Introduction 6.2 Types of Storage Devices 6.3 Busses - Connecting IO Devices to CPU/Memory. Interrupts etc. How is data transferred. 6.5 Reliability, Availability and RAID We will look at how devices (especially disks) are put together. We’ll look at how to connect IO devices to the CPU. And then we’ll look at RAID, the brainchild of Patterson and his buddies. Chap. 6 - Storage

  4. The Processor Picture Chap. 6 - Storage

  5. The Processor Picture Processor/Memory Bus PCI Bus I/O Busses Chap. 6 - Storage

  6. Processor Processor Processor Processor Registers Registers Registers Registers Cache Cache Cache Cache The Processor Picture Memory I/O Chap. 6 - Storage

  7. Types of Storage Devices In this section we will: Take a quick look at how disks work. This is only one example of IO, but we will save networks, tapes, etc. for another course. 6.1 Introduction 6.2 Types of Storage Devices 6.3 Busses - Connecting IO Devices to CPU/Memory. Interrupts etc. How is data transferred. 6.5 Reliability, Availability and RAID Chap. 6 - Storage

  8. Types of Storage Devices Disk Device Terminology • Purpose: • Long-term, nonvolatile storage • Large, inexpensive, slow level in the storage hierarchy • Bus Interface: • IDE • SCSI – Small Computer System Interface • Fibre Channel • Transfer rate • About 120 Mbyte/second through the interface bus. • About 5 Mbyte/second off of heads. • Data is moved in Blocks • Capacity • Approaching 100 Gigabytes • Quadruples every 3 years (aerodynamics) • Can be grouped together to get terabytes of data. Chap. 6 - Storage

  9. Types of Storage Devices Disk Device Terminology Example: Seagate Cheetah ST336752LC 36 Gigabytes 15,000 RPM 3.6 ms avg seek time. $699.00 4 disks, 8 heads (so 8 tracks) 71,000,000 Total Sectors 18,000 cylinders Average of 4,000 sectors/cylinder or 500 sectors / track (but different amounts on each track.) MTBF = 1,200,000 hours http://www.seagate.com/cda/products/discsales/marketing/detail/0,1121,355,00.html Chap. 6 - Storage

  10. Response time = Queue + Controller + Seek + Rot + Xfer Service time Types of Storage Devices Performance of Magnetic Disks Track Sector Cylinder Platter Head 15,000 RPM = 240 RPS => 4 ms per rev Average rotational latency = 2 ms 500 sectors per track => 0.10 ms per sector 512 bytes per sector => 5,000,000 MB / s Electronics (controller) Read Cache Write Cache Control Data Chap. 6 - Storage

  11. Busses In this section we will: Look at various bus mechanisms. In very simple terms, a bus is the connection between various chips/components in the computer. The bus is responsible for sending data/control between these various components. 6.1 Introduction 6.2 Types of Storage Devices 6.3 Busses - Connecting IO Devices to CPU/Memory 6.4 I/O Performance Measures 6.5 Reliability, Availability and RAID Chap. 6 - Storage

  12. Busses Interconnect Trends Network Channel Backplane • Interconnect = glue that interfaces computer system components • High speed hardware interfaces + logical protocols • Networks, channels, backplanes Connects Machines Devices Chips >1000 m 10 - 100 m 0.1 m Distance 10 - 1000 Mb/s 40 - 1000 Mb/s 320 - 2000+ Mb/s Bandwidth high ( 1ms) medium low (Nanosecs.) Latency low medium high Reliability Extensive CRC Byte Parity Byte Parity message-based narrow pathways distributed arbitration memory-mapped wide pathways centralized arbitration Chap. 6 - Storage

  13. Busses A Computer System with One Bus: Backplane Bus Backplane Bus Processor Memory • A single bus (the backplane bus) is used for: • Processor to memory communication • Communication between I/O devices and memory • Advantages: Simple and low cost • Disadvantages: slow and the bus can become a major bottleneck • Example: IBM PC - AT I/O Devices Chap. 6 - Storage

  14. Processor Memory Bus Processor Memory Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus I/O Bus I/O Bus Busses A Two-Bus System • I/O buses tap into the processor-memory bus via bus adaptors: • Processor-memory bus: mainly for processor-memory traffic • I/O buses: provide expansion slots for I/O devices • Apple Macintosh-II • NuBus: Processor, memory, and a few selected I/O devices • SCCI Bus: the rest of the I/O devices Chap. 6 - Storage

  15. Processor Memory Bus Processor Memory Bus Adaptor Bus Adaptor I/O Bus Backplane Bus Bus Adaptor I/O Bus Busses A Three-Bus System • A small number of backplane buses tap into the processor-memory bus • Processor-memory bus is only used for processor-memory traffic • I/O buses are connected to the backplane bus • Advantage: loading on the processor bus is greatly reduced Chap. 6 - Storage

  16. Busses Processor North/South Bridge architectures: separate busses Processor Memory Bus Director Memory “backside cache” • Separate sets of pins for different functions • Memory bus • Caches • Graphics bus (for fast frame buffer) • I/O busses are connected to the backplane bus • Advantage: • Busses can run at different speeds • Much less overall loading! Bus Adaptor I/O Bus Backplane Bus Bus Adaptor I/O Bus Chap. 6 - Storage

  17. Busses What defines a bus? Transaction Protocol Timing and Signaling Specification Bunch of Wires Electrical Specification Physical / Mechanical Characteristics – the connectors Chap. 6 - Storage

  18. Busses Synchronous and Asynchronous Bus • Synchronous Bus: • Includes a clock in the control lines • A fixed protocol for communication that is relative to the clock • Advantage: involves very little logic and can run very fast • Disadvantages: • Every device on the bus must run at the same clock rate • To avoid clock skew, busses cannot be long if they are fast • Asynchronous Bus: • It is not clocked • It can accommodate a wide range of devices • It can be lengthened without worrying about clock skew • It requires a handshaking protocol Chap. 6 - Storage

  19. Busses Busses So Far Master Slave ° ° ° Control Lines Bus Master: has ability to control the bus, initiates transaction Bus Slave: module activated by the transaction Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information. Asynchronous Bus Transfers: control lines (req, ack) serve to orchestrate sequencing. Synchronous Bus Transfers: sequence relative to common clock. Address Lines Data Lines Chap. 6 - Storage

  20. Busses Arbitration: Obtaining Access to the Bus Control: Master initiates requests Bus Master Bus Slave Data can go either way • One of the most important issues in bus design: • How is the bus reserved by a device that wishes to use it? • Chaos is avoided by a master-slave arrangement: • Only the bus master can control access to the bus: It initiates and controls all bus requests • A slave responds to read and write requests • The simplest system: • Processor is the only bus master • All bus requests must be controlled by the processor • Major drawback: the processor is involved in every transaction Chap. 6 - Storage

  21. Busses The Daisy Chain Bus Arbitrations Scheme Device 1 Highest Priority Device N Lowest Priority Device 2 • Advantage: simple • Disadvantages: • Cannot assure fairness: A low-priority device may be locked out indefinitely • The use of the daisy chain grant signal also limits the bus speed Grant Grant Grant Release Bus Arbiter Request wired-OR • Order is: • Request • Grant • Release. Chap. 6 - Storage

  22. Busses Simple Synchronous Protocol Clock Bus Request • Even memory busses are more complex than this • memory (slave) may take time to respond • it may need to control data rate Bus Grant R/W Address Cmd+Addr Data1 Data2 Data Chap. 6 - Storage

  23. Busses Asynchronous Handshake (4-phase) Write Transaction Address Data Read Request Acknowledge Master Asserts Address Next Address Master Asserts Data t0 : Master has obtained control and asserts address, direction (not read), data. Waits a specified amount of time for slaves to decode target t1: Master asserts request line t2: Slave asserts ack, indicating data received t3: Master releases req t4: Slave releases ack t0 t1 t2 t3 t4 t5 This is Fig. 6.11 Chap. 6 - Storage

  24. Busses Read Transaction Address Data Read Req Ack Master Asserts Address Next Address Slave Data t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target\ t1: Master asserts request line t2: Slave asserts ack, indicating ready to transmit data t3: Master releases req, data received t4: Slave releases ack t0 t1 t2 t3 t4 t5 Chap. 6 - Storage

  25. Busses EXAMPLE: PCI Read/Write Transactions • All signals sampled on rising edge • Centralized Parallel Arbitration • overlapped with previous transaction • All transfers are (unlimited) bursts • Address phase starts by asserting FRAME# • Next cycle “initiator” asserts cmd and address • Data transfers happen on when • IRDY# asserted by master when ready to transfer data • TRDY# asserted by target when ready to transfer data • transfer when both asserted on rising edge • FRAME# de-asserted when master intends to complete only one more data transfer Chap. 6 - Storage

  26. Busses EXAMPLE: PCI Read Transaction – Turn-around cycle on any signal driven by more than one agent Chap. 6 - Storage

  27. Interfacing I/O To The Processor How The CPU Talks To The IO • The interface consists of setting up the device with what operation is to be performed- • Read or Write • Size of transfer • Location on device • Location in memory • Then triggering the device to start the operation • When operation complete, the device will interrupt. I/O instructions (in,out) unique from memory access instructions. LDD R0,D,P <-- Load R0 with the contents found at device D, port P. Device registers are mapped to look like regular memory: LD R0,Mem1 <-- Load R0 with the contents found at device D, port P. This works because an initialization has correlated the device characteristics with location Mem1. Chap. 6 - Storage

  28. Interfacing I/O To The Processor How The CPU Talks To The IO ROM RAM Virtual Memory Pointing at IO space. target device where commands are I/O OP Device Address CPU IOC (1) Issues instruction to IOC (4) IOC interrupts CPU when done IOP looks in memory for commands (2) OP Addr Cnt Other (3) memory what to do special requests Device to/from memory transfers are controlled by the IOC directly. where to put data how much Chap. 6 - Storage

  29. Interfacing I/O To The Processor Memory Mapped I/O Some physical addresses are set aside. There is no REAL memory at these addresses. Instead when the processor sees these addresses, it knows to aim the instruction at the IO processor. ROM RAM I/O Chap. 6 - Storage

  30. Interfacing I/O To The Processor Transfer Method 1:Programmed I/O (Polling) CPU Is the data ready? busy wait loop not an efficient way to use the CPU unless the device is very fast! no Memory IOC yes read data device but checks for I/O completion can be dispersed among computationally intensive code store data done? no yes Chap. 6 - Storage

  31. Interfacing I/O To The Processor Device Interrupts • An I/O interrupt is just like the exception handlers except: • An I/O interrupt is asynchronous • Further information needs to be conveyed • An I/O interrupt is asynchronous with respect to instruction execution: • I/O interrupt is not associated with any instruction • I/O interrupt does not prevent any instruction from completion • You can pick your own convenient point to take an interrupt • I/O interrupt is more complicated than exception: • Needs to convey the identity of the device generating the interrupt • Interrupt requests can have different urgencies: • Interrupt request needs to be prioritized Chap. 6 - Storage

  32. PC saved Disable All Ints Supervisor Mode Raise priority Reenable All Ints Save registers  lw $r1,20($r0) lw $r2,0($r1) addi $r3,$r0,#5 sw $r3,0($r1)  Restore registers Clear current Int Disable All Ints Restore priority RTI  add $r1,$r2,$r3 subi $r4,$r1,#4 slli $r4,$r4,#2 Hiccup(!) lw $r2,0($r4) lw $r3,4($r4) add $r2,$r2,$r3 sw 8($r4),$r2  External Interrupt “Interrupt Handler” Restore PC User Mode Interfacing I/O To The Processor Device Interrupts • Advantage: • User program progress is only halted during actual transfer • Disadvantage, special hardware is needed to: • Cause an interrupt (I/O device) • Detect an interrupt (processor) • Save the proper states to resume after the interrupt (processor) Chap. 6 - Storage

  33. Interfacing I/O To The Processor Transfer Method 2:Interrupt Driven Data Transfer add sub and or nop CPU user program (1) I/O interrupt (2) save PC Memory IOC (3) interrupt service addr device read store ... rti interrupt service routine User program progress only halted during actual transfer. Interrupt handler code does the transfer. 1000 transfers at 1000 bytes each: 1000 interrupts @ 2 µsec per interrupt 1000 interrupt service @ 98 µsec each = 0.1 CPU seconds (4) memory Device xfer rate = 10 MBytes/sec => 0 .1 x 10-6 sec/byte => 0.1 µsec/byte => 1000 bytes = 100 µsec 1000 transfers x 100 µsecs = 100 ms = 0.1 CPU seconds Still far from device transfer rate! 1/2 in interrupt overhead Chap. 6 - Storage

  34. Interfacing I/O To The Processor Delegating I/O Responsibility from the CPU: DMA CPU sends a starting address, direction, and length count to IOC. Then issues "start". • Direct Memory Access (DMA): • External to the CPU • Act as a master on the bus • Transfers blocks of data to or from memory without CPU intervention CPU Memory IOC device IOC provides handshake signals for Peripheral Controller, and Memory Addresses and handshake signals for Memory. Chap. 6 - Storage

  35. Interfacing I/O To The Processor Transfer Method 3:Direct Memory Access Time to do 1000 xfers at 1000 bytes each: 1 DMA set-up sequence @ 50 µsec 1 interrupt @ 2 µsec 1 interrupt service sequence @ 48 µsec .0001 second of CPU time CPU sends a starting address, direction, and length count to DMAC. Then issues "start". 0 ROM CPU Memory Mapped I/O RAM Memory IOC device Peripherals IOC provides handshake signals for Peripheral Controller, and Memory Addresses and handshake signals for Memory. IO Buffers n Chap. 6 - Storage

  36. RAID • Redundant Array of Independent Disks • In this section we will: • Motivate a need to have greater reliability and availability for disk data. • Look at ways to get this greater reliability. 6.1 Introduction 6.2 Types of Storage Devices 6.3 Busses - Connecting IO Devices to CPU/Memory. Interrupts etc. How is data transferred. 6.5 Reliability, Availability and RAID Chap. 6 - Storage

  37. RAID Array Reliability • Reliability of N disks = Reliability of 1 Disk ÷ N • 1,200,000 Hours ÷ 100 disks = 12,000 hours • 1 year = 365 * 24 = 8700 hours • Disk system MTTF: Drops from 140 years to about 1.5 years! • • Arrays (without redundancy) too unreliable to be useful! Hot spares support reconstruction in parallel with access: very high media availability can be achieved Chap. 6 - Storage

  38. RAID Redundant Arrays of Disks • Files are "striped" across multiple spindles • Redundancy yields high data availability Disks will fail Contents reconstructed from data redundantly stored in the array Capacity penalty to store it Bandwidth penalty to update Mirroring/Shadowing (high capacity cost) Parity Techniques: Chap. 6 - Storage

  39. RAID Redundant Arrays of DisksRAID 1: Disk Mirroring/Shadowing recovery group • Each disk is fully duplicated onto its "shadow" Very high availability can be achieved • Bandwidth sacrifice on write: Logical write = two physical writes • Reads may be optimized • Most expensive solution: 100% capacity overhead Targeted for high I/O rate , high availability environments Probabliity of failure (assuming 24 hours MTTR) = 24 / ( 1.2 X 106 X 1.2 X 106 ) = 6.9 x 10-13 = 170,000,000 years Chap. 6 - Storage

  40. RAID Redundant Arrays of Disks RAID 3: Parity Disk 10010011 11001101 10010011 . . . P logical record 1 0 0 1 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 0 0 Striped physical records • Parity computed across recovery group to protect against hard disk failures 33% capacity cost for parity in this configuration wider arrays reduce capacity costs, decrease expected availability, increase reconstruction time • Arms logically synchronized, spindles rotationally synchronized logically a single high capacity, high transfer rate disk Targeted for high bandwidth applications: Scientific, Image Processing Chap. 6 - Storage

  41. RAID Redundant Arrays of Disks RAID 5+: High I/O Rate Parity Increasing Logical Disk Addresses D0 D1 D2 D3 P A logical write becomes four physical I/Os Independent writes possible because of interleaved parity Reed-Solomon Codes ("Q") for protection during reconstruction D4 D5 D6 P D7 D8 D9 P D10 D11 D12 P D13 D14 D15 Stripe P D16 D17 D18 D19 Targeted for mixed applications Stripe Unit D20 D21 D22 D23 P . . . . . . . . . . . . . . . Disk Columns Chap. 6 - Storage

  42. RAID-5: Small Write Algorithm 1 Logical Write = 2 Physical Reads + 2 Physical Writes D0 D1 D2 D0' D3 P old data new data old parity (1. Read) (2. Read) XOR + + XOR (3. Write) (4. Write) D0' D1 D2 D3 P' RAID Problems of Disk Arrays: Small Writes Chap. 6 - Storage

  43. RAID Subsystem Organization single board disk controller Cache array controller host host adapter single board disk controller manages interface to host, DMA control, buffering, parity logic single board disk controller physical device control single board disk controller striping software off-loaded from host to array controller no applications modifications no reduction of host performance Chap. 6 - Storage

  44. Array Controller String Controller . . . String Controller . . . String Controller . . . String Controller . . . String Controller . . . String Controller . . . RAID System Availability: Orthogonal RAIDs Data Recovery Group: unit of data redundancy Redundant Support Components: fans, power supplies, controller, cables End to End Data Integrity: internal parity protected data paths Chap. 6 - Storage

  45. RAID System-Level Availability host host Fully dual redundant I/O Controller I/O Controller Cache & Array Controller Cache & Array Controller . . . . . . . . . Goal: No Single Points of Failure . . . . . . . . . with duplicated paths, higher performance can be obtained when there are no failures Recovery Group Chap. 6 - Storage

  46. Summary 6.1 Introduction 6.2 Types of Storage Devices 6.3 Busses - Connecting IO Devices to CPU/Memory. Interrupts etc. How is data transferred. 6.5 Reliability, Availability and RAID Chap. 6 - Storage

  47. Course Summary During this course, we’ve started to learn about the details of computer architecture. Items included: Instruction Sets - especially a glimpse at the Intel instruction set. Pipelines - the gyrations necessary to speed up the processor. Memory - the various elements in the hierarchy designed to speed up the effective access to data. IO - a brief look at disks, busses, and how they are put together. Chap. 6 - Storage

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