High Level Language (HLL) Design Methodology Handel C

ECE 448 Lecture 12 High Level Language (HLL)Design MethodologyHandel C ECE 448 – FPGA and ASIC Design with VHDL

Main sources • Celoxica Ltd. • Handel-C Language Reference Manual • available on WebCT ECE 448 – FPGA and ASIC Design with VHDL

Behavioral Synthesis ECE 448 – FPGA and ASIC Design with VHDL

Behavioral Synthesis I/O Behavior Target Library Algorithm Behavioral Synthesis RTL Design Logic Synthesis Classic RTL Design Flow Gate level Netlist ECE 448 – FPGA and ASIC Design with VHDL

Need for High-Level Design • Higher level of abstraction • Modeling complex designs • Reduce design efforts • Fast turnaround time • Technology independence • Ease of HW/SW partitioning ECE 448 – FPGA and ASIC Design with VHDL

Advantages of Behavioral Synthesis • Easy to model higher level of complexities • Smaller in size source compared to RTL code • Generates RTL much faster than manual method • Multi-cycle functionality • Loops • Memory Access ECE 448 – FPGA and ASIC Design with VHDL

High-Level Languages • C/C++-Based • Handel C– Celoxica Ltd., UK • Impulse C– Impulse Accelerated Technologies • Catapult C– Impulse Accelerated Technologies • System C– The Open SystemC Initiative • Java-based • Forge – Xilinx • JHDL – Brigham Young University ECE 448 – FPGA and ASIC Design with VHDL

Other High-Level Design Flows • Matlab-based • System Generator for DSP–Xilinx • AccelChip DSP Synthesis–AccelChip • GUI Data-Flow based • Corefire–Annapolis Microsystems • RC Toolbox– DSPlogic ECE 448 – FPGA and ASIC Design with VHDL

Handel C Design Flow ECE 448 – FPGA and ASIC Design with VHDL

Design Flow Executable Specification Handel-C VHDL Synthesis EDIF EDIF Place & Route ECE 448 – FPGA and ASIC Design with VHDL

Handel-C/ANSI-C Comparisons ANSI-C HANDEL-C Handel-C Standard Library ANSI-C Standard Library Preprocessors i.e. #define Parallelism Pointers Structures Channels Side Effects i.e. X = Y++ ANSI-C Constructs for, while, if, switch Arbitrary width variables Arrays Bitwise logical operators Enhanced bit manipulation Recursion Logical operators Arithmetic operators RAM, ROM Signals Floating Point Functions Interfaces ECE 448 – FPGA and ASIC Design with VHDL

Variables ECE 448 – FPGA and ASIC Design with VHDL • Only one fundamental type for variables: int int 5 x; unsigned int 13 y; • Default types char 8 bits short 16 bits long 32 bits

Type Summary ECE 448 – FPGA and ASIC Design with VHDL

Arrays ECE 448 – FPGA and ASIC Design with VHDL • Same way as in ANSI-C int 6 x[7]; 7 registers of 6 bits wide unsigned int 6 x [4] [5] [6]; 120 registers of 6 bits wide • Index must be a compile time constant. If random access is required, consider using RAM or ROM

Internal RAMs and ROMs ECE 448 – FPGA and ASIC Design with VHDL • Using ram and rom keywords ram int 6 a [43]; a RAM consisting of 43 entries of 6 bits wide rom int 16 b [4]; a ROM consisting of 4 entries of 16 bits wide • RAMs and ROMs are accessed the same way that arrays are accessed in ANSI-C • Index need not be a compile time constant

Restrictions on RAMs and ROMs ECE 448 – FPGA and ASIC Design with VHDL • RAMs and ROMs are restricted to performing operations sequentially. Only one element may be addressed in any given clock cycle ram unsigned int 8 x [4]; x [1] = x [3] + 1; illegal if (x [0] == 0) x [1] = 1; illegal

Multi-port RAMs ECE 448 – FPGA and ASIC Design with VHDL static mpram Fred { ram <unsigned 8> ReadWrite[256]; (read/write port) rom <unsigned 8> Read[256]; (read only port) } Now we can read and write in a given clock cycle

Dual Port Memory ECE 448 – FPGA and ASIC Design with VHDL

Handel-C Language (1) ECE 448 – FPGA and ASIC Design with VHDL A subset of ANSI-C Sequential software style with a “par” construct to implement parallelism A channel “chan” statement allows for communication and synchronization between parallel branches Level of design abstraction is above RTL but below behavioral

Handel-C Language (2) ECE 448 – FPGA and ASIC Design with VHDL Each assignment and delay statement take one clock cycle Automatic generation of the state machine from an algorithmic description of the circuit in terms of parallel and sequential blocks Automatic scheduling of parallel and sequential blocks, that is the code following a group is scheduled only after that whole group has completed

Parallelism Statement Parallel blocks ECE 448 – FPGA and ASIC Design with VHDL

Channel Communication Statement Channel a b ECE 448 – FPGA and ASIC Design with VHDL

Par construct - Examples ECE 448 – FPGA and ASIC Design with VHDL

Par constructs - timing ECE 448 – FPGA and ASIC Design with VHDL

Par construct – shift register ECE 448 – FPGA and ASIC Design with VHDL

Channels ECE 448 – FPGA and ASIC Design with VHDL

Channel Communication ECE 448 – FPGA and ASIC Design with VHDL • Reading from a channel Channel ? Variable; • Writing to a channel Channel ! Expression; • No simultaneous write to or read from a single channel par par { { out ! 3; in ? x; out ! 4; in ? y; } }

Scope and Variable Sharing y w x z ECE 448 – FPGA and ASIC Design with VHDL int w; void main(void) { int x; { int y; ….. } { int z; ….. } }

Statements ECE 448 – FPGA and ASIC Design with VHDL

Bit Manipulation Operators ECE 448 – FPGA and ASIC Design with VHDL

Handel-C Example x[n] 32 32 32 G31(z) G1(z) G0(z) z-1 z-1 z-1 void polyphase() { ram int IN_WIDTH pin0_0[2], pin0_1[2], pin0_2[2], pin0_3[2]; ram int IN_WIDTH pin1_0[2], pin1_1[2], pin1_2[2], pin1_3[2]; ram int IN_WIDTH pin2_0[2], pin2_1[2], pin2_2[2], pin2_3[2]; ….. while (1) { par { padd0_0[half] = (pmult0_0[half][15] @ (pmult0_0[half] \\ 7)) + (pmult0_1[half][15] @ (pmult0_1[half] \\ 7)); padd0_1[half] = (pmult0_2[half][15] @ (pmult0_2[half] \\ 7)) + (pmult0_3[half][15] @ (pmult0_3[half] \\ 7)); pmult0_0[half] = 0; pmult0_1[half] = -7 * (pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half][7] @ pin0_1[half]); pmult0_2[half] = 109 * (pin0_2[half][7] @ pin0_2[half][7] @ pin0_2[half][7] @ pin0_2[half][7] @ if (half) { par { output[0] ! (((padd0_0[1][9] @ padd0_0[1]) + (padd0_1[1][9] @ padd0_1[1])) \\ 3); ECE 448 – FPGA and ASIC Design with VHDL

Take/drop operators ECE 448 – FPGA and ASIC Design with VHDL

Concatenation ECE 448 – FPGA and ASIC Design with VHDL

Bit selection ECE 448 – FPGA and ASIC Design with VHDL

Width operator ECE 448 – FPGA and ASIC Design with VHDL

Arithmetic Operators ECE 448 – FPGA and ASIC Design with VHDL

Relational Operators ECE 448 – FPGA and ASIC Design with VHDL

Relational Logical Operators ECE 448 – FPGA and ASIC Design with VHDL

Bitwise Logical Operators ECE 448 – FPGA and ASIC Design with VHDL

Compile Time Constant Expressions ECE 448 – FPGA and ASIC Design with VHDL

Width of results (1) ECE 448 – FPGA and ASIC Design with VHDL

Width of results (2) ECE 448 – FPGA and ASIC Design with VHDL

Example - Accumulator ECE 448 – FPGA and ASIC Design with VHDL void main(void) { unsigned int 16 sum; unsigned int 8 data; chanin input; chanout output; sum = 0; do { input ? data; sum = sum + (0 @ data); } while (data!=0); output ! sum; }

Handel C vs. C - functions Functions may not be called recursively, since all logic must be expanded at compile-time to generate hardware You can only call functions in expression statements. These statements must not contain any other calls or assignments. Variable length parameter lists are not supported. Old-style ANSI-C function declarations (where the type of the parameters is not specified) are not supported. main() functions take no arguments and return no values. Each main() function is associated with a clock. If you have more than one main() function in the same source file, they must all use the same clock. ECE 448 – FPGA and ASIC Design with VHDL

Handel-C Overview • High-level language based on ISO/ANSI-C for the implementation of algorithms in hardware • Allows software engineers to design hardware without retraining • Clean extensions for hardware design including flexible data widths, parallelism and communications • Based on Communicating Sequential Process model • Independent parallel processes • “par” construct to specify parallel computation blocks within a process • Well defined timing model • Each statement takes a single clock cycle • Includes extended operators for bit manipulation, and high-level mathematical macros (including floating point) ECE 448 – FPGA and ASIC Design with VHDL

Handel C Additional Features ECE 448 – FPGA and ASIC Design with VHDL

Prialt statement ECE 448 – FPGA and ASIC Design with VHDL

Restrictions on using Prialt statement ECE 448 – FPGA and ASIC Design with VHDL

Macros and Functions ECE 448 – FPGA and ASIC Design with VHDL

High Level Language (HLL) Design Methodology Handel C