Bruce Mayer, PE Licensed Electrical & Mechanical Engineer BMayer@ChabotCollege

1. Engineering 43 Chp14-2Op Amp Circuits Bruce Mayer, PE Licensed Electrical & Mechanical EngineerBMayer@ChabotCollege.edu

2. RC OpAmp Circuits • Introduce Two Very Important Practical Circuits Based On Operational Amplifiers • Recall the OpAmp • The “Ideal” Model That we Use • RO = 0 • Ri = ∞ • Av = ∞ • BW = ∞ • Consequences of Ideality • RO = 0  vO = Av(v+−v−) • Ri = ∞  i+ =i− = 0 • Av = ∞  v+ = v− • BW = ∞  OpAmp will follow the very Highest Frequency Inputs

3. = v 0 + RC OpAmp Ckt  Integrator • KCL At v−node • By Ideal OpAmp • Ri = ∞  i+ = i−= 0 • Av = ∞  v+ = v− = 0

4. RC OpAmp Integrator cont • Separating the Variables and Integrating Yields the Solution for vo(t) • By the Ideal OpAmp Assumptions • Thus the Output is a (negative) SCALED TIME INTEGRAL of the input Signal • A simple Differential Eqn

5. KVL = v 0 + RC OpAmp Ckt  Differentiator • By Ideal OpAmp • v−= GND = 0V • i−= 0 • KCL at v− • Now the KVL

6. RC OpAmp Differentiator cont. • Recall the Capacitor Integral Law • Recall Ideal OpAmp Assumptions • Ri = ∞  i+ = i− = 0 • Av = ∞  v+ = v− = 0 • Then the KCL • Thus the KVL • Multiply Eqn by C1, then Take the Time Derivative of the new Eqn

7. RC OpAmp Differentiator cont • Examination of this Eqn Reveals That if R1 were ZERO, Then vO would be Proportional to the TIME DERIVATIVE of the input Signal • In Practice An Ideal Differentiator Amplifies Electrical Noise And Does Not Operate well • The Resistor R1 Introduces a Filtering Action. • Its Value Is Kept As Small As Possible To Approximatea Differentiator • In the Previous Differential Eqn use KCL to sub vO for i1 • Using

8. ALL electrical signals are corrupted by external, uncontrollable and often unmeasurable, signals. These undesired signals are referred to as NOISE Signal Signal Noise Noise Aside → Electrical Noise • The Signal-To-Noise Ratio • Use an Ideal Differentiator • Simple Model For A Noisy 1V, 60Hz Sinusoid Corrupted With One MicroVolt of 1GHz Interference • The SN is Degraded Due to Hi-Frequency Noise

9. Class Exercise  Ideal Differen. • Let’s Turn on the Lites for 10 minutes for YOU to Differentiate • Given the IDEAL Differentiator Ckt and INPUT Signal • Find vo(t) over 0-10 ms • Given Input v1(t) • SAWTOOTH Wave • Recall the Differentiator Eqn R1 = 0; Ideal ckt

10. RC OpAmp Differentiator Ex. • The Slope from 0-5 mS • Given Input v1(t) • For the Ideal Differentiator • Units Analysis

11. RC OpAmp Differentiator cont. • Derivative Scalar PreFactor • A Similar Analysis for 5-10 mS yields the Complete vO OutPut InPut • Apply the Prefactor Against the INput Signal Time-Derivative (slope)

12. RC OpAmp Integrator Example • For the Ideal Integrator • Given Input v1(t) • SQUARE Wave • Units Analysis Again

13. RC OpAmp Integrator Ex. cont. • 0<t<0.1 S • v1(t) = 20 mV (Const) • The Integration PreFactor • 0.1t<0.2 S • v1(t) = –20 mV (Const) • Next Calculate the Area Under the Curve to Determine the Voltage Level At the Break Points • Integrate In Similar Fashion over • 0.2t<0.3 S • 0.3t<0.4 S

14. RC OpAmp Integrator Ex. cont.1 • Apply the 1000/S PreFactor and Plot Piece-Wise

15. Design an OpAmp ckt to implement in HARDWARE this Math Relation Design Example • Examine the Reln to find an Integrator Summer

16. The Proposed Solution Design Example • The by Ideal OpAmps & KCL & KVL &Superposition

17. Design Example • The Ckt Eqn • Then the Design Eqns • This means that we, as ckt designers, get to PICK 3 values • For 1st Cut Choose • C = 20 μF • R1 = 100 kΩ • R4 = 20 kΩ • TWO Eqns in FIVE unknowns

18. In the Design Eqns Design Example 20μ 20k 20k 100k 10k • If the voltages are <10V, then all currents should be the in mA range, which should prevent over-heating • Then the DESIGN

19. LM741 OpAmp Schematic

20. Some LM741 Specs

21. OpAmp Frequency Response • The Ideal OpAmphas infinite Band-Width so NO Matterhow FAST the inputsignals • However, REAL OpAmps Can NOT Keep up with very fast signals • The Open Loop Gain, AO, starts to degrade with increasing input frequencies

22. Gain∙BandWidth for LM741 −20db/DecadeSlope The Unity Gain Frequency, ft, is the BandWidth Spec

23. BandWidth Limit Implications • Recall the OpAmp based Inverting ckt • The NONideal Analysis yielded • Noting That All the R’s are Constant; Rewrite above as • For Very Large A

24. BandWidth Limit Implications • As Frequency Increases the Open-Loop gain, A, declines so the Limit does NOT hold in: • If • Then the Denom in the above Eqn ≠ 1 • Thus significantly smaller A DECREASES the Ideal gain • For Typical Values of the R’s the Open-Loop Gain, A, becomes important when A is on the order of about 1000

25. Gain∙BandWidth for LM741 • Frequency significantly degrades Amplification Performance for Source Frequencies > 10 kHz

26. Voltage Swing Limitations • Real OpAmps Can NOT deliver Unlimited Voltage-Magnitude Output • Recall the LM741 Spec Sheet that show a Voltage Output Swing of about ±15V • For Source Voltages of ±20 V • If the Circuit Analysis Predicts vo of more than the Swing, the output will be “Clipped” • Consider the Inverting Circuit:

27. Vswing Clipping • Since the Real OutPut can NOT exceed 15V, the cosine wave OutPut is “Clipped Off” at the Swing Spec of 15V ENGR43_Lec14b_OpAmp_V_Swing_Plot_1204.m

28. Short-Ckt Current Limitations • Real OpAmps Can NOT deliver Unlimited Current-Magnitude Output • Recall the LM741 Spec Sheet that shows an Output Short Circuit Current of about 25mA • If the Circuit Analysis Predicts io of more than This Current, the output will also be “Clipped” • Consider the Inverting Circuit:

29. CurrentSaturation • Since the Real OutPut can NOT exceed 25mA, the cosine wave OutPut is “Clipped Off” at the Short Circuit Current spec of 25mA ENGR43_Lec14b_OpAmp_Current_Saturation_Plot_1204.m

30. Slew Rate = dvo/dt • For a Real OpAmp we expect the OutPut Cannot Rise or Fall Infinitely Fast. • This Rise/Fall Speed is quantified as the “Slew Rate”, SR • Mathematically the Slew Rate limitation • The 741 Specs indicate a Slew Rate of

31. Slew Rate = dvo/dt • If dvin/dt exceeds the SR at any point in time, then the output will NOT be Faithful to input • The OpAmp can NOT “Keep Up” with the Input • Consider the Example at Top Right • Then the Time Slope of the Source

32. Slew Rate = dvo/dt • The Maximum value of dvS/dt Occurs at t=0. Compare the max to the SR • Thus the source Rises & Falls Faster than the SR • When the Source Slope exceeds the SR the OpAmp Output Rises/Falls at the SR • This produces a STRAIGHT-LINE output with a slope of the SR when the source rises/falls Faster than the SR until the OpAmp“Catches Up” withthe Ideal OutPut

33. Slew Rate = dvo/dt

34. Full Power BandWidth • The Full Power BW is the Maximum Frequency that the OpAmp can Deliver an Undistorted Sinusoidal Signal • The Quantity, fFP, is limited by the SLEW RATE • Determine This Metric for the LM741 • The 741 has a max output, Vom, of ±12V • Applying a sinusoid to the input find at full OutPut power (Full Output Voltage) • Recall the Slew Rate

35. Full Power BandWidth • Taking d/dt of the OpAmp running at Full Output • Thus the maximum output change-rate (slope) in magnitude • Recall ω = 2πf • Setting |dvo/dt|max = to the Slew Rate

36. Full Power BandWidth • Isolating f in the last expression yields fFP: • From the LM741 Spec Sheet • SR = 0.5 V/µS • |Vomax|min = 12V • Then fFP:

37. Full Power BandWidth • Thus the 741 OpAmp can deliver UNdistorted, Full Voltage, sinusoidal Output (±12V) for input Frequencies up to about 6.63 kHz

38. WhiteBoard Work • Let’s Work These Probs • Choose C Such That Find Energy Stored on Cx

39. All Done for Today OpAmpCircuitDesign

40. Engineering 43 Appendix Bruce Mayer, PE Registered Electrical & Mechanical EngineerBMayer@ChabotCollege.edu

46. Practical Example • Simple Circuit Model For a Dynamic Random Access Memory Cell (DRAM) • Note How Undesired Current Leakage is Modeled as an I-Src • Also Note the TINY Value of the Cell-State Capacitance (50x10-15 F)

47. Practical Example cont • During a WRITE Cycle the Cell Cap is Charged to 3V for a Logic-1 • Thus The TIME PERIOD that the cell can HOLD the Logic-1 value • The Criteria for a Logic “1” • Vcell >1.5 V • Now Recall that V = Q/C • Or in terms of Current • Now Can Calculate the DRAM “Refresh Rate”

48. Practical Example cont.2 • Consider the Cell at the Beginning of a READ Operation • When the Switch is Connected Have Caps in Parallel • Then The Output • Calc the Best-Case Change in VI/O at the READ