Hardware Acceleration

1. Hardware Acceleration February 2006

2. The Problem • Verification tools have not kept pace with the incredible rate at which design sizes are growing. • Each verification stage has its own methodology, tools, models and user inteface. • Embedded Software debug/integration is started late after first silicon/prototype. Design complexity System-on-a-chip verification, 2001 – P.Rashinkar

3. Methodologies Prototyping Faster speed, closer to final product Emulation Hardware Accelerated Simulation Simulation Basicverificationtool Semi-formal Verification Formal Verification Bigger coverage

4. Hardware-Accelerated Simulation • Simulation performance is improved by moving the time-consuming part of the design to hardware. • Usually, the software simulation communicates with FPGA-based hardware accelerator. Hardware Accelerator Simulation environment Testbench Module 2 is synthesized & compiled into FPGAs Module 0 Module 1 Module 2

5. Hardware-Accelerated Simulation • Pros • Fast (100K cycles/sec) • Cheaper than hardware emulation • Debugging is easier as the circuit structure is unchanged. • Not an Overhead : Deployed as a step stone in the gradual refinement • Cons (Obstacles to overcome) • Set-up time overhead to map RTL design into the hardware can be substantial. • SW-HW communication speed can degrade the performance. • Debugging of signals within the hardware can be difficult.

6. Emulation • Imitating the function of another system to achieve the same results as the imitated system. • Usually, the emulation hardware comprises an array of FPGA’s (or special-type processors) and interconnection scheme among them. • About 1000 times faster than simulation. Prototyping Emulation Hardware Accelerated Simulation Simulation

7. Emulation • User logic design is mapped to emulation board with multiple FPGA’s or special processors. • The emulation board has external interconnection hardware that emulates the pins of final chip. Emulation hardware with multiple FPGAs Logic design Design mapping & > & + External pins

8. Emulation • Pros • Fast (500K cycles/sec) • Verification on real target system. • Cons • Setup time overhead to map RTL design into hardware is very high. • Many FPGA’s + resources for debugging  high cost • Circuit partitioning algorithm and interconnection architecture limit the usable gate count.

9. Prototyping • Special (more dedicated and customized) hardware architecture made to fit a specific application. • Pros • Higher (than emulation) clock rate (over 1M cycles/sec) due to specific design of prototyping board. • Components as well as the wiring can be customized for the corresponding application. • Can be carried along. (Hardware Emulation? Forget it!) • Cons • Not flexible for design change (Every new prototype requires a new board architecture. / Even a small change requires a new PCB.)

10. Survey Does your company use HW emulators/accelerators like Cadence Quickturn Palladium, Mentor IKOS/Meta Systems, Verisity Axis, Tharas, Pittsburgh Simulations, EVE, or Aptix? (10/25/05 ) Resource : http://www.deepchip.com/items/dvcon05-15.html

11. Products Cadence - PALLADIUM • Simulation acceleration and in-circuit emulation in one system • natively supports Verilog, VHDL, System Verilog, SystemC, SystemC Verification Library, OVL, and PSL/Sugar assertions. • Dynamic probes/events allow interactive debug during run-time • Comprehensive verification with "live" data • Support for assertions in hardware with no performance degradation • High Capacity - • Provides up to 100x-10,000x RTL performance ( run four days of simulations over lunch at 100x). • Compiles up to 30 million gates per hour on a single workstation • Maximum capacity of 256 million gates • Supports up to 32 users in local or remote access • Highest throughput for HW/SW co-verification

12. Products Mentor - VStationTBX • Single verification environment for simulation and verification • High-performance verification accelerator for designs and testbenches • Built on standard languages: SystemC, SystemVerilog, C/C++ • Behavioral Verilog testbench and memory compiler • VHDL and Verilog RTL debug • HDL acceleration 10x-100x faster than co-simulation • Accelerates the entire design process with advanced techniques, such as assertions and transactions

13. Products Verisity - Xtreme Server • Support SpeXtreme - direct compilation of e testbenches • Multi-Purpose – • Seamlessly integrates emulation, acceleration, and simulation into a single verification environment • Provides a configurable platform for early system-level integration • Emulates behavioral objects with reconfigurable behavioral processors • High Capacity - • Supports designs of up to 50M ASIC gates • Provides memory of up to 12 GB • Supports up to 4,656 IOs • Allows up to 12 simultaneous users • Easy-to-Use - Preserves native simulation debugging environment by supporting all HDL constructs, PLI calls, and testbenches

14. Products Verisity - SpeXtreme

15. Other solution • Homebrew with FPGAs – • Partition design to number of FPGAs. • Use FPGA on-chip processors or configurable processors to drive testbench. • Pros • Low cost solution. • fast • Cons • Most embedded processor compilers supports C/C++ languages. • Requires two verification environments. • Need to establish debug connection between WS and FPGAs

16. Conclusions Hardware Acceleration/Emulation Simulation Acceleration Verification Acceleration Project Acceleration

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