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Hardware Acceleration for Stereo-Vision Algorithms

Hardware Acceleration for Stereo-Vision Algorithms. Henning Sahlbach, Sean Whitty, Peter Rüffer, Rolf Ernst sahlbach | whitty | rueffer | ernst@ida.ing.tu-bs.de Technical University of Braunschweig, Germany. Outline. Introduction Targeted algorithms Targeted hardware accelerator

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Hardware Acceleration for Stereo-Vision Algorithms

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  1. Hardware Acceleration forStereo-Vision Algorithms Henning Sahlbach, Sean Whitty, Peter Rüffer, Rolf Ernst sahlbach | whitty | rueffer | ernst@ida.ing.tu-bs.de Technical University of Braunschweig, Germany

  2. Outline • Introduction • Targeted algorithms • Targeted hardware accelerator • Conclusion / Future work

  3. Introduction Cooperation project of Volkswagen and IDA Target: FPGA based acceleration of image processing algorithms Algorithms from autonomous driving domain Non-accelerated algorithm implementations available at VW IDA has experiences in hardware acceleration for image processing IDA and VW: Perfect match ;)

  4. Targeted algorithms Possible algorithms Stereo-vision: Calculation of disparity vector Motion detection Based on sum of absolute differences (SAD), known from FlexFilm project Based on sum of squared differences (SSD), similar to SAD Based on normalized cross correlation (NCC), complex and computation intensive but delivers best results Corner / Edge Detection Used to improve motion detection results Structure from Motion (in far future)

  5. Current project: Motion detection Calculate motion vectors from preceding and following image Re-use algorithms implemented in FlexFilm project (SAD, exhaustive search) Different application requirements Smaller block size (8x8 instead of 16x16 pixels) Smaller image sizes (1300x1000 instead of 2048x1556 pixels) Larger search area (-32/+31 instead of -8/+7) More frames per second (60 FPS instead of 24 FPS) Demanding application with similar hardware requirements to FlexFilm project

  6. Implementation concept Calculate horizontal vectors by pipelining search blocks of 64 processing elements Huge chip area required Calculate vertical vectors by time multiplexing of search blocks Fast FPGAs required Complex control logic Implementation started in internship ME 1 ME 2 ME n-1 ME n n n n n

  7. Outline Introduction Targeted algorithms Targeted hardware accelerator Conclusion / Future work

  8. Hardware accelerator requirements Key requirements PCIe for host PC integration, at least 4 lanes Huge and fast FPGAs Interfaces for CameraLink connection needed Support for Windows and Linux Price limit: 8000 € per board Physical limitations: Should be usable in a standard PC No board available that satisfies all constraints Only HiTech Global boards satisfies all technical requirements Problem: Windows and Linux support from HiTech Global is very expensive

  9. HiTech Global HTG-LX330T

  10. HTG-LX330T features Technical features Xilinx Virtex 5 LX330T / SX240T FPGA 68 pairs of LVDS I/O for CameraLink connection Up to 2 GB of SO-DIMM DDR2 Memory 8-Lane PCI Express End-Point 2 Gigabit Ethernet Ports 2 SATA Ports 256 MB Flash Memory Price: $10.000 (LX330) / $12.000 (SX240) HiTech Global sells a DMA engine with Linux and Windows drivers (total: $21.000), exceeds budget

  11. Conclusion / Future work Good progresses in algorithm development in internship Despite high prices HiTech Global solution will be purchased (hopefully soon) No comparable alternatives For funding second contract with VW was prepared VW is very interested and curious regarding hardware acceleration Project will most probably be continued next year Many possible algorithms that can be accelerated Very interesting application domain

  12. Thank you for your attention

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