Universal Reconfigurable Processing Platform for Space

1. Universal Reconfigurable Processing Platform for Space Presented by Dorian Seagrave Gordonicus LLC

2. Introduction An increasing number of spacecraft system engineers and scientists are demanding: • More processing power • Flexible architecture • Standard / COTS communication interfaces • Multiple Mission Modes / Reconfigurability • Small form factor • Mission hardware reuse • Low power • High speed SERDES • High Reliability MAPLD 2009 Gordonicus LLC

3. No blind and buried vias Flight Board meets NASA and IPC 6012 class 3 standards Aeroflex LEON3FT UT699 Features This hardware platform provides these needs by combining: • Reconfigurable State-of-the-Art High Speed Data Processing Capabilities • 1553 • 100 Mb Ethernet • 200 Mb Spacewire routers • COTs Interfaces: cPCI (33MHz) & High Speed SERDES on P2 • A Rad Hard LEON3FT Processor • 1 Gbyte protected SDRAM STS125 Mission MAPLD 2009 Gordonicus LLC

4. LEON3FT Processing Applications • Guidance, Navigation and Control (GNC) • Control and Data Handling (CDH) • Xilinx Monitoring and Reconfiguration MAPLD 2009 Gordonicus LLC

5. Xilinx Processing Applications • High Speed DSP Algorithm Processing • Image Processing • Pose Estimation Algorithms • Communications / Radio • Data Encryption / Decryption • Waveform Processing • Instrument Data Validation and Compression • Application Reconfigurable While in Flight MAPLD 2009 Gordonicus LLC

6. 5 PROCESSORS LEON3FT ASIC AeroFlex UT699 SPARCTM V8/LEON 3FT 66 MHz Up to 52.8 MIPS Floating Point and MMU TID: 300 krad (Si) SEL Immune >110 MeV-cm2/mg 4 x 350 MHz PowerPC™ 405 Heritage Implementation Dual Xilinx QV4 FX60 32 bit RISC processors 700+ DMIPS TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO) STANDARD I/O INTERFACES 10 SPACEWIRE PORTS Up to 200Mbps (Configurable) Supports Cross stapping Multiple configurations CompactPCI 32 Bit, 33MHz Master and Slave Mode Supported PCI 2.2 Compliant NASA Hypertronics connectors Mil-Std-1553 A/B Mil-Std-1553 BC/RT/MT Based on the Actel Core1553 IP CONSOLE PORT LEON3FT UART Rate configurable SPECIFICATIONS MEMORY 1 GByte SDRAM • Reed Solomon Protected corrects for 2 nibble upsets 8 GByte FLASH • stored in two banks 16 Gbit SDRAM • 4Gbits per PPC405 2 MBbyte SRAM • Protected (Self Scrubbing) 32 KByte PROM SMALL SIZE DIMENSIONS • Standard 3U cPCI • Single slot front panel configuration supports: 4 SpaceWire, 1553 A/B , Console port and Debug. • Dual slot front panel configuration supports additional SpaceWire ports. • CONFIGURABLE I/O • 10 RS422/LVDS Transmit Ports • Xilinx configured (Quad redundant) 10 RS422/LVDS Receive Ports • Xilinx configured (Quad redundant) 39 Xilinx Backplane I/O 12 Actel I/O 2 LEON GPIO 2 Backplane Spacewire Backplane Ethernet FRONT PANEL DEVELOPMENT / DEBUG PORTS DEVELOPMENT • LEON3FT 10T/100 Ethernet port • Xilinx 10T/100 Ethernet port DEBUG • LEON Debug Serial Port • RTAX Debug Serial Port • Xilinx Debug Serial Port • JTAG LOW POWER LEON3FT • 2.5Volt Core Xilinx • 1.2Volt Core MAPLD 2009 Gordonicus LLC

7. LEON 3FT AeroFlex UT699 SPARCTM V8 66 MHz Up to 52.8 MIPS Floating Point and MMU TID: 300 krad (Si) SEL Immune >110 MeV-cm2/mg LEON3FT PROCESSOR & MEMORY MEMORY 1GByte SDRAM • Reed Solomon Protected corrects for 2 nibble upsets 8GByte FLASH • Stored in two banks 2MBbyte SRAM • Protected (Self Scrubbing) 32KByte PROM MAPLD 2009 Gordonicus LLC

8. LEON3FT PROCESSOR & MEMORY 52.8 MIPS 2MByte SRAM (Internal EDAC) Actel RTAX LEON3FT Aeroflex UT699 4GByte FLASH 4GByte FLASH 32KB PROM 1GByte SDRAM (Reed Solomon) TID: 300 krad (Si) SEL Immune >110 MeV-cm2/mg MAPLD 2009 Gordonicus LLC

9. Quad redundant or independent PPC processing Mixed operating systems Partial or Full reconfiguration CONFIGURABLE LOGIC per FX60 Logic Cells: 56,880 Slices: 25,880 Distributed RAM: 395kb XtremeDSP Slices: 128 Block RAM: 4,176Kb Xilinx QV4 FX60 FPGAs & MEMORY • EMBEDDED PowerPC 405 • 350 MHz operation • 16 KB instruction cache • 16 KB data cache • 32 bit RISC processors • 700+ DMIPS • TID: 250 krad (Si) • SEL Immune >110 MeV-cm2/mg • SEFI: 1.5E-6 Upsets/device/day (GEO) • MEMORY • 8Gbit SDRAM • 2Gbits per PPC405 Gordonicus LLC

10. XILINX PPC405 PROCESSORS & MEMORY 512MByte SDRAM 512MByte SDRAM Xilinx QV4 FX60 700 DMIPs PPC 405 PPC 405 200Mbps SpaceWire(4) Xilinx QV4 FX60 LEON3FT Aeroflex UT699 Dual Xilinx QV4 FX60 PPC 405 PPC 405 Based on Heritage Architecture Implementation 512MByte SDRAM 512MByte SDRAM TID: 250 krad (Si) SEL Immune >110 MeV-cm2/mg SEFI: 1.5E-6 Upsets/device/day (GEO) MAPLD 2009 Gordonicus LLC

11. Xilinx DSP Processing Architecture Node Interconnections Top Xilinx QV4 FX60 • High Speed Communication • Between Nodes • External Memory Resource Sharing PPC0 PPC1 Flexible Design Options : PPC2 PPC3 • 4 Designs = • Quad Redundant or Single Strand Bottom Xilinx QV4 FX60 • 2 Designs = 1 Design per Xilinx • 1 Design TMRed using both Xilinx MAPLD 2009 Gordonicus LLC

12. Xilinx Reconfiguration WITHOUT disruption to the other nodes Xilinx Resources consist of 4 nodes. Node = PPC + surrounding FPGA fabric. Top Xilinx QV4 FX60 PPC0 PPC1 SelectMap SDRAM Control Logic FLASH PPC2 PPC3 • A Singe Node can be reconfigured with • PPC Operating system Bottom Xilinx QV4 FX60 • PPC application code or • Xilinx fabric reconfiguration MAPLD 2009 Gordonicus LLC

13. STANDARD INTERFACES • CompactPCI • Console Port Async UART • 1553 • SpaceWire MAPLD 2009 Gordonicus LLC

14. CompactPCIMIL-STD-1553 A/B LEON3FT Console Port MAPLD 2009 Gordonicus LLC

15. SpaceWire Ports 10 Front Panel SpW Router 5 Port F R O N T P A N E L RTAX 200Mbps 200/100/50 Mbps SpW Router 5 Port LEON3FT 4 Backplane 200Mbps 200Mbps Configurable Xilinx C P C I P 2 200Mbps Configurable Front Panel Conn. Thru-hole Jumpers 2 Backplane via Jumpers MAPLD 2009 Gordonicus LLC

16. Configurable I/O What if my instrument interface is not SpaceWire? What if I need a custom interface on the backplane? ie: I2C What if I forgot to add a control line to a device? MAPLD 2009 Gordonicus LLC

17. 73 User Defined I/O Sync / Async Serial IF C P C I P 2 12 User Defined I/O I2C 1 Wire Protocol ACTEL F R O N T P A N E L LVDS OR RS422 2 GPIO LEON3FT 10 Bi-Dir User Defined I/O LVDS OR RS422 LVDS OR RS422 39 User Defined I/O Xilinx LVDS OR RS422 LVDS OR RS422 MAPLD 2009 Gordonicus LLC

18. Development & Debug Ports • LEON 10T/100 Ethernet MII Interface (FRONT Panel or Backplane) • Xilinx 10T/100 Ethernet MII Interface (FRONT Panel or Backplane) • LEON and Xilinx Ethernet ports can be connected • LEON Dedicated Debug Port (DSU) • Xilinx I/O to be used as serial ports • Xilinx JTAG • LEON JTAG • ACTEL JTAG All Debug / Development ports are accessible from the front panel. Facilitates Hardware Reuse GSE reconfiguration without opening the box MAPLD 2009 Gordonicus LLC

19. RTAX 2000 CONFIGURATIONS • CG624 Package Supports ALDEC RTAX development Suite. • Flexible architecture using Gaisler/Aeroflex Cores MAPLD 2009 Gordonicus LLC

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21. Application DSP Xilinx Fabric PPC 405 uP DSP Xilinx Fabric DSP Xilinx Fabric SpaceWire PPC 405 uP PPC 405 uP DSP Xilinx Fabric PPC 405 uP 512MB 512MB 512MB 512MB LEON3FT SpaceWire DownLink0 SpW Router MissionCrd0 MissionCrd2 RTAX DownLink1 SpW Router MissionCrd1 MissionCrd3 MAPLD 2009 Gordonicus LLC

22. Availability Contact Aeroflex Colorado Springs MAPLD 2009 Gordonicus LLC

23. Future…. Xilinx SIRF V5 Xilinx SIRF V5 MAPLD 2009 Gordonicus LLC

24. Next Effort LEON3FT 16 MBytes EEPROM 8 Port SpW Router 16 GBytes FLASH 1 GByte SDRAM 1553 3U cPCI MAPLD 2009 Gordonicus LLC

25. Gordonicus LLC www.gordonicus.com Hardware Gordon Seagrave • gordon@gordonicus.coom Dorian Seagrave • dorian@gordoniucs.com Software Peter Cavender • peter@gordonicus.com John Gemmill • john@gordonicus.com MAPLD 2009 Gordonicus LLC