An Architecture for Reconfigurable Computing in Space

1. An Architecture for Reconfigurable Computing in Space Robert F. Hodson1, Kevin Somervill1, John Williams2, Neil Bergman2, Rob Jones3 1NASA LaRC, 2University of Queensland, 3ASRC Aerospace

2. RSC Goals & Objectives • To develop the next generation high performance space-qualified computing system leveraging… • Field Programmable Gate Arrays FPGAs • Intellectual Property (IP) • Soft cores, processors • COTS software architectures • Multi-processor • Specialized • Meet Strategic Challenges • Reconfigurability • Modularity • First step towards the next generation avionics suite

3. Why Reconfigurable Computing with Soft Cores & Custom Logic • Soft cores readily available for rad-tolerant FPGAs • Custom co-processors can improve performance on average by 5.8X • Power consumption can also be reduced on average by 57% • Reconfiguration allows many designs without hardware redesign – reducing cost • Making this approach competitive with current space computing systems • Source: R. Lysecky and F. Vahid, “A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning,” Design Automation and Test in Europe (DATE), March 2005

4. Scalable Architecture Multiple interconnected general purpose processing nodes with optimized custom logic attached for special purpose processing.

5. Physical Concept Stacks of reconfigurable processing modules (RPMs) similar to a ruggedized version of a PC104+ stack. Modules, which make up a stack will be RPMs, Command Control Module (CCM), Network Module (NM), etc. Physical design will support launch loads, radiation shielding, and conduction cooling. Modules STACKS

6. Command Control Module (CCM) Reconfigurable Processing Module (RPM) Reconfigurable Processing Module (RPM) Reconfigurable Processing Module (RPM) Network Module (NM) Power Module (PM) BUS Modular Technology • Modules will be combined to build RSC systems • Designs will be based on rugged small form factor modular stackable technology • Allows mixing and matching of appropriate modules to meet mission requirements • Planned modules • Reconfigurable Processing Module (RPM) • Command/Control Module (CCM) • Network Module (NM) • Power Module (PM)

7. Multiple Interconnected RSC Stacks

8. Software Architecture MPI uCLinux RSC plans to deliver a complete system with hardware, system software, development software, and a demonstration application.

9. Reconfigurable Processing Module RPM Xilinx FPGA (V4FX60) Data Cache uB Parallel IO Custom Logic Instr Cache SERDES (2.5 Gbps) Config Memory Switch Serial IO SLout SLin SDRAM (512 MB) Frame Buf ConfigMgr Bus NVRAM (FLASH or CRAM 32MB min) SDRAM I/F PCI I/F NVR I/F NIC Actel FPGA PCI Bus 33MHz 32/64 Bits

10. RPM Features • Xilinx logic is triplicated and scrubbed • Custom cache design (MicroBlaze cache not used) • Caches will be scrubbed • SDRAM is SECDED protected and scrubbed. • Rad-Hard NVRAM is an issue • Compressed code image and configuration is stored in NVRAM. It is copied to SDRAM and decompressed after reset. • If the system has multiple MicroBlaze processors they each have separate memory space in the same physical memory. • Custom logic can communicate via FSL or OPB • PCI interface supports Master/Target/DMA

11. ReceivingCPU or NM SendingCPU Application/MPI INTR Message Message Sockets message Transport IP Address and Size of Datagram Data Data PHdr PHdr UDP packet Network IP IP Data Data PHdr PHdr Internet Protocol datagrams DMA Engine NIC NIC Network Req INTR Data Linkand Physical Pull PCI Address and Size of Datagram ACK Buses RSC Protocol Stack

12. Controller Req queue Communication Event Sequence 2. Message send request. 9. Interrupt to source CPU. Buffer can now be released. CPU Source NIC Source RPM 3. IP address is translated to PCI address of destination. SDRAM PCI I/F IP2PCIMapping Message Buffer 5. Destination NIC pulls (DMAs) message into destination RPM’s memory. 1. Datagram is built in memory. PCI Bus PCI I/F IP2PCIMapping SDRAM 4. PCI Address of message on source RPM sent to destination NIC. Message Buffer Controller 8. Destination NIC tells source NIC “message received.” Req queue CPU Destination NIC 7. Message processed. Destination RPM 6. Message received interrupt sent to CPU.

13. Command & Control Module The Command and Control Module (CCM) provides the primary command interface to the system. If also controls the system bus initialization and boot process. CCM Memory NVRAM Discrete IO Memory Controller Test port IO Controller Reset uController 1553 Command I/F System Reset Hub Configuration and Code Selects Power Mgmt Power Good PCI Backend I/F PCI Arbiter PCI Master/Target PCI

14. Network Module Design To/from other stacks SERDES SERDES SERDES SERDES Link I/F Routing Lookup Additional Link I/Fs Control From Link Interfaces To Other Link Interfaces From Link Interfaces Network Module (NM) provides an interface to other RSC stacks. It buffers and routes IP packets based on routing information loaded during system initialization. Serialized links provide a high-bandwidth interconnect to other systems. Routing Lookup Control DMA PCI I/F Actel AX2000

15. RSC Robotic Demonstrator • Demonstrate reconfigurable technology on a challenging real-time control and processing application • Tele-operated robot with multiple sensors • Stereo camera • Omni camera • IR camera • X-Ray florescence sensor • Several others

16. RSC Team • Core Team Members • NASA Langley Research Center (Lead) • NASA Goddard Space Flight Center • The University of Queensland • ARSC Aerospace • Jefferson Lab (DoE) • Starbridge Systems • Department of Defense • Affiliate Members • Air Force Research Laboratory • SEAKR Engineering • Imagination Engines