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PLC Development 2010g

PLC Development 2010g. Michael Kellow Kathleen Manuel James Kemp. www.2010g.info. Overview. Scope Completed Tasks Current Progress Communication Software Hardware Future Plans. 2. Scope.

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PLC Development 2010g

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  1. PLC Development 2010g Michael Kellow Kathleen Manuel James Kemp www.2010g.info

  2. Overview • Scope • Completed Tasks • Current Progress • Communication • Software • Hardware • Future Plans 2

  3. Scope Research, develop and construct an industry standard PLC (programmable logic controller) for teaching purposes. 3

  4. Project Structure 4

  5. Completed Tasks Deliverables from Project 1 • Project plan • Survey Report • Seminar 1 • Work Progress Report • Webpage 5

  6. Current Progress Completed Tasks From Project 2 • Hardware – 70% Complete • Software – 75% Complete • Communications – 70% Complete 6

  7. Communications Protocol 7

  8. Communications Protocol Start/End => tells the Modbus whether a new message needs to be processed and when it ends Address => Server (slave) address Function => Type of action to perform Data => Contains the request and response parameters CRC => Error checking 8

  9. Valid Transaction 9

  10. Invalid Transaction 10

  11. Modbus Functions Common Modbus Function Codes 11

  12. Communications Protocol 12

  13. Communications Protocol 13

  14. Communications Protocol Serial Communication • EIA-232 and EIA-485 • Basic Test of Serial Coms • PC (master) and ATMEGA32 (slave) running through the RS-232 and RS-485 serial communications 14

  15. Current Status Completed • Source code Interpreter • Abstract Syntax Tree • Memory Structure • Execution Tree • 20% Instructions Remaining • Timer Interface • Counter Interface • Status Registers • Uploading Interface 15

  16. Design Decision Compiler • Faster • Simpler Interpreter • Better Structure • Real Time • Extendable 16

  17. PLC Memory Structure • Fixed memory addresses • Approximately 2k of SRAM utilised • PLC S3:24 • C S3[24]; 17

  18. Complex Memory Structure 18

  19. Memory Addressing • Direct Addressing T4:03 • Indexed Addressing #T4:03 • Indirect Addressing T4:[N7:02] • Indexed Indirect Addressing #T4:[N7:02] 19

  20. Memory Addressing Direct Memory Addressing Timer T4:03 # = T4:07 … 0 15 199 Direct Memory Addressing Index Register S:24 = 4 20

  21. Source Code = 21

  22. Ladder Structure typedefstructladder_ts { unsigned charladderId; charladderName[255]; rung_t*firstRung; structladder_ts*nextLadder; } ladder_t; 22

  23. Rung Structure typedefstructrung_ts { unsigned char rungId; charrungName[255]; inst_t*firstInst; structrung_ts*nextRung; } rung_t; 23

  24. Instruction Structure typedefstructinst_ts { char name[4]; inst_fn_t*func; arg_t*args; structinst_ts*nextLadder; } inst_t 24

  25. Argument Structure typedefstructarg_ts { char memType[4]; void *location; char offset; boolindexed; structarg_ts*indirect; structarg_ts*nextArg; } arg_t; 25

  26. Executing PLC pInstruction->func( pInstruction->args); while ( pLadder ) { while ( pRung ) { while ( pInstruction && pInstruction->func(pInstruction->args)) { pInstruction = pInstruction->nextInst; } pRung = pRung->nextRung; } pLadder = pLadder->nextLadder; } 26

  27. Hardware 27

  28. Power Supply • 230v AC Input • 3.3v DC Output • 5v DC Output • 12v DC Output • Switch Mode – Linear Combination 28

  29. Control Module • Processor – Atmel XMega256-D3 • RS232 • RS485 • USB • ISP 29

  30. Digital Output Module • Processor Atmel Mega8515 • 8 Channel • Open Collector Output • LED Output Indicator 30

  31. Modules To Come • Digital Input • Relay Output • Analogue Input 31

  32. Future Goals Interfacing all three parts together Demonstration Set Documentation Project Poster 32

  33. Questions

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