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EECS 362

EECS 362. Group 2: Kevin Cheung Michael Glowacki Alex Romine Dave Sexton. Arithmetic Instructions. ADDI ADDUI SUBI SUBUI. ADD ADDU SUB SUBU MULT MULTU DIV DIVU. rd, rs 1 , rs 2. rd, rs 1 , immediate. Arithmetic Instructions. ADDU SUBU. ADD SUB.

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EECS 362

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  1. EECS 362 Group 2: Kevin Cheung Michael Glowacki Alex Romine Dave Sexton

  2. Arithmetic Instructions • ADDI • ADDUI • SUBI • SUBUI • ADD • ADDU • SUB • SUBU • MULT • MULTU • DIV • DIVU rd, rs1, rs2 rd, rs1, immediate

  3. Arithmetic Instructions • ADDU • SUBU • ADD • SUB • All instructions in R-type format. • ADD/SUB treat the contents of source registers as signed (two’s complement) integers. • ADD/SUB generate arithmetic overflow when result of operations are (> 231 – 1) or (< -231). • ADDU/SUBU treats contents in source registers as unsigned integers • ADDU/SUBU do not generate arithmetic overflow.

  4. Arithmetic Instructions • ADDI • SUBI • ADDUI • SUBUI • All instructions in I-type format. • 16-bit immediate is extended to 32-bit. • Sign extended for ADDI/SUBI and zero extended for ADDUI/SUBUI.

  5. Arithmetic Instructions • MULTU • DIVU • MULT • DIV • All instructions in R-type format. • Only use floating point registers. • MULT/DIV treat contents in source register as signed integers and MULTU/DIVU treat them as unsigned integers.

  6. Logical Instructions • AND • OR • XOR rd, rs1, rs2 • ANDI • ORI • XORI rd, rs1, immediate • LHI rd, immediate

  7. Logical Instructions • LHI (Load High Immediate) • Places 16-bit immediate into the most significant portion of the destination register and fills remaining portion of destination register with 0’s.

  8. Branch • BEQZ • BNEZ • BEQZ branches when rs1 is 0. • BNEZ branches when rs1 is not 0. rs1, name • BFPT • BFPF name • BFPT branches when FPSR is 1. • BFPF branches when FPSR is 0.

  9. Reusable Components • Can reuse most of the ALU with some modifications. • SLL shifter can be reused. • 32-bit MUX’s • Register bank can be reused but needs to be expanded.

  10. Discussion of Complications • Limits to pipelining: Hazards prevent nextinstruction from executing during its designated clock cycle. – Structural hazards: HW cannot support this combination of instructions. – Data hazards: Instruction depends on result of prior instruction still in the pipeline. – Control hazards: Pipelining of branches & other instructions that change the PC.

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