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Analog Electronics Workshop Stability

Analog Electronics Workshop Stability. March 13, 2013. The Culprits. Capacitive Loads!. Cable/Shield Drive!. MOSFET Gate Drive!. Reference Buffers!. High Feedback Network Impedance!. High-Source Impedance or Low-Power Circuits!. Attenuators!. Transimpedance Amplifiers!.

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Analog Electronics Workshop Stability

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  1. Analog Electronics WorkshopStability March 13, 2013

  2. The Culprits Capacitive Loads! Cable/Shield Drive! MOSFET Gate Drive! Reference Buffers! High Feedback Network Impedance! High-Source Impedance or Low-Power Circuits! Attenuators! Transimpedance Amplifiers!

  3. Recognize Stability Issues • Oscilloscope - Transient Domain Analysis: • Oscillations or Ringing • Overshoots • Unstable DC Voltages • High Distortion

  4. Recognize Stability Issues • Gain / Phase Analyzer - Frequency Domain: Peaking, Unexpected Gains, Rapid Phase Shifts

  5. What causes amplifier stability issues?

  6. Fundamental Cause of Amplifier Stability Issues • Too much delay in the feedback network

  7. Quick Bode Plot Review

  8. Poles and Bode Plots • Pole Location = fP • Magnitude = -20dB/Decade Slope • Slope begins at fP and continues down as frequency increases • Actual Function = -3dB down @ fP • Phase= -45°/Decade Slope through fP • Decade Above fP Phase = -84.3° • Decade Below fP Phase = -5.7°

  9. Zeros and Bode Plots • Zero Location = fZ • Magnitude = +20dB/Decade Slope • Slope begins at fZ and continues up as frequency increases • Actual Function = +3dB up @ fZ • Phase = +45°/Decade Slope through fZ • Decade Above fZ Phase = +84.3° • Decade Below fZ Phase = 5.7°

  10. Op-Amp Loop Gain Model VOUT/VIN = Acl = Aol/(1+Aolβ) If Aol >> 1 then Acl ≈ 1/β Aol: Open Loop Gain β: Feedback Factor Acl: Closed Loop Gain

  11. Stability Criteria using 1/β & Aol At fcl: Loop Gain (Aolb) = 1 Rate-of-Closure @ fcl = (Aol slope – 1/β slope) *20dB/decade Rate-of-Closure @ fcl = STABLE **40dB/decade Rate-of-Closure@ fcl = UNSTABLE

  12. Stabilizing Unity Gain Buffer with Capacitive Load

  13. Unity Gain Buffer

  14. Capacitive Loads – Unity Gain Buffers - Theory

  15. Unity Gain Buffer Determine the issue: Pole in AOL!! ROC = 40dB/decade!! Phase Margin 0!! NG = 1V/V = 0dB

  16. Stability Options Unity-Gain circuits can only be stabilized by modifying the AOL load

  17. Method 1: Riso - Theory

  18. Method 1: Riso - Design Ensure Good Phase Margin: 1.) Find: fcl and f(AOL = 20dB) 2.) Set Riso to create AOL zero: Good: f(zero) = Fcl for PM ≈ 45 degrees. Better: f(zero) = F(AOL = 20dB) will yield slightly less than 90 degrees phase margin fcl = 222.74kHz f(AOL = 20dB) = 70.41kHz

  19. Method 1: Riso Theory: Adds a zero to the Loaded AOL response to cancel the pole

  20. Method 1: Riso When to use: Works well when DC accuracy is not important, or when loads are very light

  21. Method 1: Riso - Disadvantage Disadvantage: Voltage drop across Riso may not be acceptable

  22. Riso Lab • Simulation • Measurement

  23. TINA Exercise-Stability

  24. TINA Exercise-Stability • Vin Settings • Square Wave Settings

  25. TINA Exercise-Stability • Analysis->Transient • View->Separate Curves

  26. TINA Exercise-Stability • Open switch and re-run transient analysis • Stable, but DC offset

  27. NI myDAQ Exercise-Riso Populate U1 with OPA627 Ensure J2 is installed

  28. NI myDAQ Exercise-Riso • Launch FGEN • FGEN Settings • Square Wave • Frequency=5kHz • Amplitude=0.2Vpp • Signal Route=AO(0) • Run

  29. NI myDAQ Exercise-Riso • Launch Scope • Scope Settings • Source = AI(0) • Scale V/Div = 50mV • Time/Div = 50us • Trigger Type = Edge • Run • Change Acquisition Mode to Run Once • Click Run for each acquisition

  30. NI myDAQ Exercise-Riso Lab Results TINA Results

  31. NI myDAQ Exercise-Stability Lab Results-High Resolution

  32. NI myDAQ Exercise-Riso Remove J2 This puts Riso in signal path Vpp=189.11mV Repeatedly remove and insert J2 Notice output swing

  33. What about DC offset? Remember the voltage drop across Riso causes DC inaccuracy

  34. Method 2: Riso + Dual Feedback

  35. Method 2: Riso + DF Theory: Features a low-frequency feedback to cancel the Riso drop and a high-frequency feedback to create the AOL pole and zero.

  36. Method 2: Riso + DF When to Use: Only practical solution for very large capacitive loads ≥ 10uF When DC accuracy must be preserved across different current loads

  37. Riso+DF Lab • Measurement

  38. NI myDAQ Exercise Move OPA627 from U1 to U2

  39. NI myDAQ Exercise-Riso+DF • Launch FGEN • FGEN Settings • Square Wave • Frequency=100Hz • Amplitude=0.2Vpp • Signal Route=AO(1) • Run

  40. NI myDAQ Exercise-Riso+DF • Launch Scope • Scope Settings • Source = AI(1) • Scale V/Div = 50mV • Time/Div = 2ms • Trigger Type = Edge • Run • Change Acquisition Mode to Run Once • Click Run for each acquisition

  41. NI myDAQ Exercise-Riso+DF Riso+DF Riso *Note: Reduced frequency due to Riso+DF settling time

  42. Further Reading Presentation Article Series

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