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Latches CS370 –Spring 2003

Latches CS370 –Spring 2003. Section 4-2 Mano & Kime. Sequential Logic. Combinational Logic Output depends only on current input Sequential Logic Output depends not only on current input but also on past input values Need some type of memory to remember the past input values.

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Latches CS370 –Spring 2003

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  1. LatchesCS370 –Spring 2003 Section 4-2 Mano & Kime

  2. Sequential Logic • Combinational Logic • Output depends only on current input • Sequential Logic • Output depends not only on current input but also on past input values • Need some type of memory to remember the past input values

  3. Circuits that we have learned so far Information Storing Circuits Timed “States”

  4. Storing Information Inverters Buffers

  5. Can’t change the stored value!

  6. !S Q !Q !R !S-!R Latch !S !R Q !Q 1 0 0 0 0 1 1 0 1 1 1 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

  7. !S Q !Q !R !S-!R Latch !S !R Q !Q 0 0 0 0 0 1 1 0 1 1 1 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

  8. !S Q !Q !R !S-!R Latch !S !R Q !Q 0 1 0 0 0 1 1 0 1 1 1 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

  9. !S Q !Q !R !S-!R Latch !S !R Q !Q 0 1 0 0 0 1 1 0 1 1 1 0 Set 0 1 0 1 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

  10. !S Q !Q !R !S-!R Latch !S !R Q !Q 1 1 0 0 0 1 1 0 1 1 1 0 Set 0 1 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

  11. !S Q !Q !R !S-!R Latch !S !R Q !Q 1 1 0 0 0 1 1 0 1 1 1 0 Set 0 0 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

  12. !S Q !Q !R !S-!R Latch !S !R Q !Q 1 1 0 0 0 1 1 0 1 1 1 0 Set 1 0 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

  13. !S Q !Q !R !S-!R Latch !S !R Q !Q 1 0 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 0 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

  14. !S Q !Q !R !S-!R Latch !S !R Q !Q 1 0 0 0 0 1 1 0 1 1 1 0 Set 0 1 Reset 1 1 0 1 Store 1 0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

  15. !S Q !Q !R !S-!R Latch !S !R Q !Q 0 1 0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set 0 1 Reset 1 0 0 1 Store 1 0 Q0 !Q0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

  16. !S Q !Q !R !S-!R Latch !S !R Q !Q 1 0 0 0 0 1 1 0 1 1 1 1 Disallowed 1 0 Set 0 1 Reset 1 1 0 1 Store 1 0 Q0 !Q0 X Y nand 0 0 1 0 1 1 1 0 1 1 1 0

  17. S-R Latches

  18. S-R Latch Simulation

  19. S - R Latch with a Clock Signal (Sequential)

  20. S CLK R S R CLK !S !R Q !Q S-R Latch !S Q !Q !R 0 0 1 1 1 Q0 !Q0 Store 0 1 1 1 0 0 1 Reset 1 0 1 0 1 1 0 Set 1 1 1 0 0 1 1 Disallowed X X 0 1 1 Q0 !Q0 Store

  21. D S R CLK Q !Q D CLK Q !Q 0 0 1 Q0 !Q0 Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 !Q0 Store 0 1 0 1 1 1 1 0 X 0 Q0 !Q0 D Latch S !S Q CLK !Q !R R

  22. D CLK Q !Q 0 1 0 1 1 1 1 0 X 0 Q0 !Q0 D Latch S !S D Q CLK !Q !R R Note that Q follows D when the clock in high, and is latched when the clock goes to zero.

  23. Does NOT latch z = z $ x = 0 $ 1 = 1 D Latch Latches on following edge of clock y CLK D x Q z x E CLK y z

  24. D Latch Use narrow pulse y CLK D x Q z x E CLK y z Does latch z = z $ x = 0 $ 1 = 1 If x remains high, successive clock pulses will toggle z

  25. D Latch with Transmission Gates

  26. D Pulse-narrowing circuit CLK D NCK Q !Q D CLK Q !Q 0 1 0 1 1 1 1 0 X 0 Q0 !Q0 0 0 1 1 1 0 X 0 Q0 !Q0 D Flip-Flop S !S Q NCK !Q !R R

  27. Pulse-Narrowing Circuit

  28. D Q CLK !Q D CLK Q !Q 0 0 1 1 1 0 X 0 Q0 !Q0 D Flip-Flop Positive edge triggered D gets latched to Q on the rising edge of the clock.

  29. D Q CLK !Q D Flip-Flop pulse width CLK setup time hold time y z propagation delay

  30. SR Master-Slave Flip-Flop S R CLK Q !Q 0 0 1 Q0 !Q0 Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 !Q0 Store

  31. J-K Flip-Flop J K CLK Q !Q 0 0 Q0 !Q0 0 1 0 1 1 0 1 0 1 1 Toggle X X 0 Q0 !Q0 J Q CLK !Q K

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