Lecture 25: Interconnect Modeling

1. Lecture 25: Interconnect Modeling EECS 312 Reading: 8.3 (text), 4.3.2, 4.4.1-4.4.4 (2nd edition) EECS 312

2. Last Time • Simultaneous switching noise is a key problem for off-chip drivers • Drive them as slowly as allowed • General interconnect characteristics • Local wires and global wires • Many metal levels, connect with vias • Capacitance is the primary parasitic • Area, fringing, interwire components • Interwire dominates today • Both simple and complex models exist to compute capacitance as a function of wire geometry EECS 312

3. Lecture Overview • Interconnect resistance • IR drop/Electromigration • RC delay models EECS 312

4. Resistance & Sheet Resistance L R = r T W Sheet Resistance L R T R R 1 2 W Resistance seen by current going from left to right is same in each block EECS 312

5. Bulk Resistivity Aluminum was dominant until ~2000 Copper has gradually taken over in the past 4-5 years Copper is pretty much as good as it gets EECS 312

6. Interconnect Resistance Resistance scales poorly – Full scaling calls for reduction in width and thickness by S each generation R ~ S2 for a fixed line length and material! Called reverse scaling wires get slower when smaller while devices get faster EECS 312

7. Polycide Gate Mosfet EECS 312

8. Impact of New Materials • IBM back-end copper process at left • Yields 12% improvement over an aluminum process in a PowerPC design Transistor EECS 312

9. RI Introduced Noise EECS 312

10. Power and Ground Distribution EECS 312

11. IR Drop in a High-Speed Design EECS 312

12. Electromigration • Migration of metal atoms in conductors which pass large DC current densities • Large current densities lead to fast moving eletrons that can rip metal atoms off their sites • This leads to open circuits and short circuits between adjacent wires • MTTF: mean time to failure • How long can we pass a constant current through a wire before it fails? • Exponentially dependent on temperature and material type (ex: Al vs. Cu) • Linear to quadratic dependence on current density EECS 312

13. Electromigration Results Limits DC current densities to ~ 106 A/cm2In a 1mm x 1mm wire  10mA EECS 312

14. Evolution of Interconnect Modeling • Before 1990, wires were thick and wide while devices were big and slow • Large wiring capacitances and device resistances • Wiring resistance was << device resistance • Model wires as capacitances only • In the 1990s, scaling theory led to smaller and faster devices and smaller, more resistive wires • Reverse Scaling properties of wires! • RC models became necessary • In the 2000s, frequencies are high enough so that inductance is a major component of total impedance EECS 312

15. Global interconnect delay grows EECS 312

16. Lumped RC model of a wire EECS 312

17. RC Delay EECS 312

18. RC Models EECS 312

19. RC Propagating Wavefront Step response of a distributed RC wire as a function of location along wire and time EECS 312

20. Delay expressions Assumes step input Vin We will typically have a load capacitance CL at node Vout EECS 312

21. Summary/Key Points • Wire resistivity gets worse as wires get smaller (reverse scaling, different than device delay) • Power distribution becomes more difficult due to IR drops and higher current densities • Lumped wire delay overestimates actual delay (distributed) • Because the entire capacitance is NOT charged through the full wire resistance • Wire RC delay increases quadratically with line length as both R and C rise linearly • This has implications on how to reduce RC delay EECS 312

22. How to reduce RC delay • Since RC delay is quadratic with length, reducing length is key • Note: 22 = 4 and 1+1 = 2 but 12 + 12 = 2 source sink source sink L = 2 units EECS 312

23. Repeaters Repeater EECS 312

24. Repeaters Impact Repeaters are simply large inverters inserted along a global interconnect to reduce the RC delay EECS 312

25. The Elmore Delay EECS 312

26. Penfield-Rubinstein-Horowitz EECS 312

27. Capacitive Crosstalk Noise • Crosstalk noise high-level description • Simple lumped model, step through it slowly • Give results EECS 312

28. Cross-sectional view EECS 312

29. High level view of crosstalk noise EECS 312

30. Noise Pulses can be large EECS 312

31. Simple Noise Model (Rubio) Model derivation: no line resistance considered, Tr is rise time of aggressor signal, R is the effective driver resistance of the victim (good approx, demonstrate using I-V curves) EECS 312

32. Linear Resistance Assumption Slope here is fairly constant with Vgs=Vdd (operating point for NMOS holding output to GND) Inverse of this slope ~ Reff Replace the victim driver by a linear resistor Only problem – if noise gets too big, the approximation becomes worse (R grows) EECS 312

33. How to Battle Capacitive Crosstalk Unrealistic – need tight packing to reduce chip area, cost EECS 312