OK, we are now ready to begin Chapter 2 of our text

1. OK, we are now ready to begin Chapter 2 of our text • We will begin looking at some preliminary stuff • Then we will look at the the Intel IA-32 (CISC) • Then we will concentrate on the MIPS 32 (RISC) Note: A number of the slides I will use for Patterson & Hennessy material are adapted, with permission, from slides of a computer engineering colleague: Professor Mary Jane Irwin of Penn State

2. Where is the Market? Millions of Computers

3. ISA Type Sales Millions of Processor

4. Moore’s Law • In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 24 months (i.e., grow exponentially with time). • The million transistor/chip barrier was crossed in the 1980’s. • 2300 transistors, 1 MHz clock (Intel 4004) - 1971 • 16 Million transistors (Ultra Sparc III) • 42 Million transistors, 2 GHz clock (Intel Xeon) – 2001 • 55 Million transistors, 3 GHz, 130nm technology, 250mm2 die (Intel Pentium 4) - 2004 • 140 Million transistor (HP PA-8500)

5. Processor Performance Increase Intel Pentium 4/3000 DEC Alpha 21264A/667 DEC Alpha 21264/600 Intel Xeon/2000 DEC Alpha 5/500 DEC Alpha 4/266 DEC Alpha 5/300 DEC AXP/500 IBM POWER 100 HP 9000/750 IBM RS6000 MIPS M2000 SUN-4/260 MIPS M/120

6. DRAM Capacity Growth 512M 256M 128M 64M 16M 4M 1M 256K 64K 16K

7. Computer Instruction Formats • Three operand e.g. Opcode Source1, Source2, Destination • Two operand e.g. Opcode Source1, Source2Destination One operand is used as Source & Destination • One operand e.g. Opcode Source Result is deposited in an Accumulator

8. The Intel IA 32

9. History of the IA-32 (Intel) 1971 – 4004 built by Intel as a calculator engine 1972 – 8008 introduced as an 8 bit computer 1974 – 8080 an 8 bit (16 address bit) enough power to build a computer around it – Altair 8800, IMSAI 8080, Osborne I (first portable computer 1981) 1976 – 8085 8080 with two interrupts 1978 – 8086 16 bit machine using enhanced 8080 instr & Reg 1980 - 8087 8086 floating pt co-processor 1981 - 8088 8 bit external data bus 1982 – 80186 & 80286 the later was the engine for the first IBM PC, added memory management to become a multiuser machine 1985 – 80386 32 bit machine with 32 bit address space 1989 – 80486 multiprogramming, pseudo GPR machine 1992 – Pentium & Pentium Pro (1995) higher performance 1997 - Added MMX media extentions 1999 – Added another 70 instructions 2001 – Added another 144 instructions 2003 - Amdahl architecture increased address space to 64 bits and breaks legacy chain 2004 – Intel adopts AMD64 architecture with slight addition Building a legacy nightmare !

10. IA-32 Registers

11. IA-32 Registers

12. IA-32 Flags Register

13. Example IA-32 Instruction Format

14. Sample IA-32 Instruction Formats Note: Instruction lengths vary from 1 to 17 bytes

15. The MIPS 32

16. RISC - Reduced Instruction Set Computer • RISC philosophy (keep it simple!) • fixed instruction length(s) (one word?) • load-store instruction sets (don’t do anything else) • limited addressing modes • limited operations • MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC, Intel (Compaq), Alpha, … • Instruction sets are measured by how well compilers use them as opposed to how well assembly language programmers use them Design goals: speed, cost (design, fabrication, test, packaging), size, power consumption, reliability, memory space (embedded systems)

17. 3 Instruction Formats: all 32 bits wide R format OP rs rd sa funct rt I format OP rs rt immediate J format OP jump target MIPS R3000 Instruction Set Architecture (ISA) • Instruction Categories • Computational • Load/Store • Jump and Branch • Floating Point • coprocessor • Memory Management • Special Registers R0 - R31 PC HI LO

18. 2. Operand: Base addressing op rs rt offset Memory word or byte operand base register MIPS Addressing Modes 1. Operand: Register addressing op rs rt rd funct Register word operand 3. Operand: Immediate addressing op rs rt operand 4. Instruction: PC-relative addressing op rs rt offset Memory branch destination instruction Program Counter (PC) 5. Instruction: Pseudo-direct addressing Memory op jump address || jump destination instruction Program Counter (PC)

19. MIPS Register Convention

20. MIPS 32 “Card”

21. 5 5 5 32 32 32 MIPS Register File Register File • Holds thirty-two 32-bit registers • Two read ports and • One write port 32 bits src1 addr src1 data src2 addr 32 locations dst addr • Registers are • Faster than main memory • But register files with more locations are slower (e.g., a 64 word file could be as much as 50% slower than a 32 word file) • Read/write port increase impacts speed quadratically • Easier for a compiler to use • e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack • Can hold variables so that • code density improves (since register are named with fewer bits than a memory location) src2 data write data write control

22. Fetch PC = PC+4 Exec Decode MIPS Organization Processor Memory Register File 1…1100 src1 addr src1 data 5 32 src2 addr 32 registers ($zero - $ra) 5 dst addr read/write addr 5 src2 data write data 32 230 words 32 32 32 bits branch offset read data 32 Add PC 32 32 32 32 Add 32 4 write data 0…1100 32 0…1000 32 4 5 6 7 0…0100 32 ALU 0 1 2 3 0…0000 32 word address (binary) 32 bits 32 byte address (big Endian)