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ADP5022 LDO Filtering Guide

ADP5022 LDO Filtering Guide. ANALOG-DEVICES – STP/IPS Group 2/17/2009. Suggested Schematic.

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ADP5022 LDO Filtering Guide

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  1. ADP5022 LDO Filtering Guide ANALOG-DEVICES – STP/IPS Group 2/17/2009

  2. Suggested Schematic The above schematic shows the complete filter solution where L1, R1 and C1 form the network for the 2nd order low-pass filter targeting the Analog circuit low frequency sensitivity. Z1 is an optional ferrite bead that reduces the high frequency noise coming from the Digital circuit clocks and harmonics to pollute LDO and Analog circuits.

  3. Filter Equivalent Circuit • The equivalent circuit shows: • Capacitors with equivalent series resistance • Omitted from C1 since being much lower than R1 • Inductor with series winding resistance • Resistive load • Other board and package parasitic components are nor considered and will affect the filter performance at higher frequency values

  4. Transfer Function Derivation From the transfer function above it can be noted that there are two zero at: FZ1 = 1/(2*πC1R2) FZ2 = 1/(2*πC2RESR2) Because RESR2 is very small the FZ2 zero occurs at high frequency. FZ1 can be position, by choosing R1, to control the filter peaking.

  5. Transfer Function Response Analyzed case where: L = 10uH, C1 = 10uF, R1 = 2.7Ω, C2 = 1uF, RESR2 = 0.36Ω The curve matches the Spice Simulation (See slide #8, magenta curve)

  6. Target Filter Specification • Reduce noise in the 1kHz to 200-kHz Band  From LDO PSRR • Filter tuned to suppress noise above 100kHz • Minimize the number of components and package size used • Take advantage of the available bypass capacitors

  7. Filter I – RLC Filter • Requires one Inductor, one resistor and one capacitor • Proposed inductor (TY CBMF1608T100) is available in 0603 case • C4 is a 0603 10uF, 6.3V, X5R Ceramic capacitor. A 4.7uF cap in 0402 could used however the large capacitance change with the bias voltage could cause filter peaking. • R1 is a 0201 chip resistor

  8. Simulation Results – Filter version I (C1,C2) • Optimal response is achieved with L1 = 10uH, C2 = 10uF and R1 = 2.7ohms. See magenta Curve • C2 is the 1uF bypass capacitor already present on the Analog circuit • FT is placed around 50-kHz, it was considered that from 1-kHz to 100-kHz the LDO low noise and high performance in this band does not require additional filtering. This helps also to keep the component to a reasonable size.

  9. Capacitor considerations Capacitor in this example is Taiyo-Yuden: JMK107BJ106MA in 0603 case. The DC Bias curve shows that the real capacitance decreases 55% with 3.3V applied. This, in addition to nominal tolerance and change with temperature can lead to a large capacitance change that will affect the filter behavior. The plot below show the filter change when varying the filter capacitor from 10uF to 1uF. ~-55%

  10. Filter II – Using 1uF Bypass capacitor Needs only one 0603 inductor Needs one 0603 inductor and one 0201 resistors.

  11. Simulation Result – Filter Version II (Only C2) • High peaking (+15dB) when using the bypass capacitor as part of the filter • Adding a series resistor damps the filter peaking but makes the bypass function useless • Filter is not as effective as the two caps version

  12. Additional filter on the digital rail • A ferrite bead is a cost effective using minimal board area • Suppression starts at few MHz and peaks at 150-MHz • Proposed filter uses Taiyo-Yuden: • BK1005HW601 DCR = 0.6 Ω – 300mA • BK1005HS102 DCR = 0.58 Ω – 300mA • Both available in 0402 case • This filter is not effective below 1-MHz • It prevent noise generated from the Digital section to pollute the Analog rail.

  13. Conclusions • The most effective solution, that covers the entire frequency range of interest, requires a RLC filter on the Analog section and a ferrite bead on the digital side. • It is not recommended to use only the bypass capacitor for the RLC filter because of the peaking centered around 50-kHz. • The proposed RLC filter is effective from 70-kHz upward and relies on the LDO PSRR and Noise performance below 70-kHz. • The RLC filter cutoff frequency can be decreased at the expenses of larger Inductor, it is suggested to perform systems test to verify if this is needed. • The ferrite bead is optional when the RLC filter is used • The presented simulation and model do not consider higher order parasitic (i.e. package and board parasitic inductance and capacitance) these will normally affect the filtering at much higher frequency and should not cause trouble. • After system testing it can determined if only a ferrite bead, from LDO output to the Digital is enough, relying on the LDO PSRR and noise performance to guarantee a clean power to the analog circuit. • Board routing and grounding are important elements to consider for optimal noise performance, especially at high frequency.

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