1 / 15

Shunt-LDO update

Shunt-LDO update. Laura Gonella Physikalisches Institut Uni Bonn. Outline. LDO mode Rout investigations Cref to generate Vref Enabled Shunt-LDO mode with Rext = 10k Ω FE-I4 powering with the regulators. Rout summary.

huong
Download Presentation

Shunt-LDO update

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Shunt-LDO update Laura Gonella Physikalisches Institut Uni Bonn

  2. Outline • LDO mode • Rout investigations • Cref to generate Vref • Enabled Shunt-LDO mode with Rext = 10kΩ • FE-I4 powering with the regulators

  3. Rout summary • Load regulation measurements showed an output impedance of about 150mOhm • Investigations done so far can exclude • Problems with test system • Temperature effects • Process variation • What is left to check • The gain of the error amplifier (A) • Simulations with corner and temperature done already, look fine • Try to change the biasing by overriding the Vbp: higher biasing current corresponds to higher A. Check what is the influence of A on the Rout • The Ron of the pass transistor • The on-chip wiring resistance

  4. Rout Vs. Vbp • The load regulation measurement does not change for different Vbp • The gain of the error amplifier does not seem to be the problem

  5. Vout Vs. Vref • Vout generation for different Vref, with and without the load

  6. Cref to generate Vref • Maurice´s suggestion

  7. Cref measurement • Connect Vout to the VDDA and still provide the Vref externally to check the Iout value • Rout = 289MOhm, Vcref = 0.766V -> Iout = 2.65uA seems OK

  8. Vref provided via Cref • When the Cref is used to generate the Vref the LDO does not start • The result compares very well with the one from the measurement done with Vref = 0V and resistive load (120Ohm) • Start-up circuit is needed

  9. Enabled Shunt-LDO mode with Rext = 10KΩ • Use the device in Shunt-LDO mode but power it with a voltage • Use an Rext of 10KΩ to set a small shunt current • Rint is left floating • This is done because a constant current flowing in the regulator helps to reduce transients on the Vin lines when transients on the load happen • Smaller transient on the Vin are desirable to limit the max Vin • Better for Vdrop on cables • Better for regulator safety

  10. Voltage generation • The voltage generation when using the regulator as Shunt-LDO with a voltage at the input works fine, as in LDO mode • The current through the device increases up to 160mA at Vin = 2.0V • In Shunt-LDO mode Vin = IinRext • For Vin = 1.943V, Iin = 158mA: Rext = 12.3KΩ

  11. Load regulation • The load regulation works as in LDO mode • The increase of Vout for Iload < Iin is expected and understood (see slides 12 and 13)

  12. Iload = 0A • When switching on the regulator the current through it is defined by Vin = IinRext • Iin flows through the pass transistor and the shunt to the ground of the regulator. From here it flows to the ground of the board. Due to the resistance of the wirebonds and of the PCB traces there is IR drop on the ground line proportional to Iin • The effective Vref seen by the regulator decreases and thus also Vout • This can be observed in the voltage generation without load IR Board gnd

  13. Iload > Iin • When starting to take a load current from the device less and less current flows through the shunt to the chip gnd, and IR decreases • The effective Vref seen by the regulator increases and thus Vout increases • When Iload > Iin, most of the current flows through the load • Only ~3mA flow thought the shunt and to the chip gnd • This is what is observed in the load regulation measurement. • For Iload < Iin Vout increases • For Iload > Iin Vout is the same as in LDO mode because the IR drop is negligible IR

  14. Powering FE-I4 with the Shunt-LDO • Work has started to power the FE-I4 with the regulators • First use direct powering to check the board and the chip • The chip is powered via the regulators on the adapter card as a standard SCC • However • 1 VDDA and 1 VDDD, 1 GND • 1x 10uf and 1x 0.1uf per power rail USBpix

  15. Status • Communication with the chip established • Write/read registers work fine • Digital and analog scans (just got to) work fine • Still a few things to cross check though... • Next to do: try powering configurations to confirm Abder´s simulations • Hopefully some results on Wednesday

More Related