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Astronomical Array Control & Acquisition System

Astronomical Array Control & Acquisition System at NAOC Zhaowang Zhao Binxun Ye Research Labs for Astronomy National Astronomical Observatories, Chinese Academy of Science June 17 , 2005. SYTEM PERFORMANCE.

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Astronomical Array Control & Acquisition System

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  1. Astronomical Array Control & Acquisition System at NAOCZhaowang Zhao Binxun YeResearch Labs for AstronomyNational Astronomical Observatories,Chinese Academy of Science June 17 , 2005

  2. SYTEM PERFORMANCE 1 Network based system. can be controlled remotely 2 Operate many kind CCD chips such as EEV, ATMEL, KODAK, SITE, FAIRCHILD, etc 3 Used the NIOS II family of embedded processors make the Camera has splendid features 4 Single chip FPGA Produces all of the signals and commands controlled by the master clock. 5 Logic and Analog circuits are synchronized completely and cuts off the noise dramatically.

  3. Intelligent Control Using Nios II embedded processor for designers accustomed to using stand-alone microprocessors and microcontrollers 10M/100M EtherNet Based Image Acquisition All of the control command through EtherNet. Voltage monitoring 12 bits ADC to measure all voltages. Temperature monitoring Very easy to upgrades and expand any control command

  4. System Performance MULTI-READ OUT MODES *Full Frame *Drift Scan by NEW IDEA *Frame Transfer *Binning *Windows

  5. CCD Controller

  6. Cryo Tiger Cooler

  7. EMBEDDED PROCESSOR CONTROL

  8. EMBEDDED PROCESSORSTRUCTURE

  9. NIOS PERFORMANCE • Nios Processor by Using Cyclone Device EP1C20FC400 device • SRAM (1 Mbyte in two banks of 512 Kbytes, 16-bit wide) • SDR SDRAM (16 Mbytes, 32-bit wide) • Flash (8 Mbytes) • EPCS4 Serial Configuration Device (4 Mbits) 10/100 Ethernet physical layer/media access control (PHY/MAC) • Ethernet connector (RJ-45) • Two serial connectors (RS-232 DB9 port)

  10. ALTERA FPGA • Cyclone family: • Work clock rates 250Mhz • EP1C20FC400 • Logic Elements: 20,060 • Total RAM Bits: 294,912 • Maximum user I/O pins: 301 • Power supply 1.5V and 3.3V • Package: BGA 400

  11. HARD WARE DESIGN

  12. NIOS EMBEDDED PROCESSOR DESIGN

  13. INSIDE STRUCTURE

  14. CCD CONTROLLER OUTLINE

  15. CCD CONTRLLER TEST CCD CONTROLLER DURING TEST

  16. CryoTiger Cooler TEST

  17. CCD Controller TEST DEWAR

  18. ALL of PCBs USED IN CCD VME –Similar BUS

  19. VME –Similar BUS Features • Standard VME BackBoard Can not Meet Astronomical Controller Requirements • 6 Layer PCB • 10 Kinds Power Supply Pins with Large Current Line • Separated Analog and Digital Ground plane • Standard 96 Pin connector • 6 Slots

  20. NIOS INTERFACE BOARD

  21. EMBEDDED PROCESSOR BOARD

  22. NIOS PROCESSOR and INTERFACE BOARD

  23. CCD ANALOG BOARD

  24. CCD DRIVEN CLOCK BOARD

  25. PRE-AMP BOARD

  26. POWER SUPPLY BOARD

  27. Control Software • All Control Software written by Visual C++ • Operate system is WIN XP or WIN2000

  28. MAIN CONTROL PROGRAM

  29. INITIAL and ETHERNET SETUP

  30. DRIVEN CLK SOFT SETUP

  31. BIAS SOFT SETUP

  32. Multi- CCDs Controlled by One Host

  33. Test Result • Read out noise: 4ADU at 500K Speed • Gain : 2.1 electrons/ADU • Fill well : 270K electrons in MPP • Linearity: 0.99997 • Transfer Efficiency: 0.999998 (Horizontal) • Power supply: VCC, +5VA, ± 12V , ± 15V , ±30V

  34. THANK YOU

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