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Alicia, Kyle, Yanqing Dept. of Electrical Engineering, University of Virginia April 10, 2013

Deliberate Practice Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design. Alicia, Kyle, Yanqing Dept. of Electrical Engineering, University of Virginia April 10, 2013. Motivation. Energy minimization for BSNs Operate circuits in sub-threshold Tradeoffs

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Alicia, Kyle, Yanqing Dept. of Electrical Engineering, University of Virginia April 10, 2013

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  1. Deliberate PracticeVariation-Resilient Building Blocks forUltra-Low-Energy Sub-Threshold Design Alicia, Kyle, Yanqing Dept. of Electrical Engineering, University of Virginia April 10, 2013

  2. Motivation • Energy minimization for BSNs • Operate circuits in sub-threshold • Tradeoffs • Sensitivity to variation • Performance

  3. Metrics for Evaluation • Energy Consumption • Gate Delay • Delay Variation • Robustness • Noise Margins (output swing) • Area overhead

  4. Attacking the Problem

  5. Research Questions • How do you design sub-threshold standard cells capable of MHz operation that are variation-resilient?

  6. Answers from Week 2 • Use technologies meant for sub-threshold (MITLL) • Use minimum sized standard cells to trade off energy and performance • Use different logic families (e.g. NAND only or not CMOS) • Custom standard cell library (PyCell?) • Use redundancy in logic paths (like RAZOR). Have a reliability vs. area tradeoff. • Increase the length of the transistors. Hurts performance but reduces energy.

  7. Paper’s Solutions • Focus on standard cells • Low-Vttransistors • Improved performance

  8. Research Questions • For an inverter, what design choices can we do to make it variation resilient? • Area overhead • Delay Variation • Robustness • Noise Margins (output swing)

  9. Answers from Week 2 • Adjust sizing to balance the P to N ratio • Mixed Vt inverter • Schmitt trigger inverter • Mixed-length NMOS

  10. Paper’s Solutions • Focus on standard cells • NMOS Stacking in gates • Can relax PMOS sizing • Decreases the delay variation • Balance N/PMOS strengths to maximize noise margin • Get rid of sizing with transmission gate logic

  11. NMOS Stacking

  12. Research Questions • After considering the inverter, what other techniques can we apply to other standard cells? • Combinational • Sequential

  13. Answers from Week 2 • Transmission gate based cells for less variation

  14. How to Expand to Logic Gates? • Problem is weak P/N ratio • Can be solved with double stack NMOS • Ratio still high (~6) • Ratio technology dependent • Solution: always have both types of transistor • TX-gate based

  15. Comparison of Methods

  16. References • Process Variations, University of Maryland, Advanced VLSI Design:http://www.csee.umbc.edu/~cpatel2/links/640/lectures/lect10_process_var.pdf • Reynders, N.; Dehaene, W., "Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.59, no.12, pp.898,902, Dec. 2012.

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