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Overview

Explore LC-3's memory layout, I/O programming, subroutines, traps mechanism, and interrupt support. Learn about stack implementation for recursion, subroutine execution, and push/pop methods. Discover how the LC-3 system handles interrupts and program status.

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Overview

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  1. Overview • I/O – memory mapped programmed / interrupt driven • Traps mechanism & RET • Subroutines & JSR & JSRR & RET • Interrupt mechanism & RTI

  2. LC-3 has Memory Mapped I/O LC-3 Memory Layout: x0000 – x00FF Trap vectors (Supports Software Interrupts) x0020 [x0400] GETC (Read Char from Keyboard) x0021 [x0430] OUT (Write Character to Console) x0022 [x0450] PUTS (Write string to Console) x0023 [x04A0] IN (Prompt, input character from Keyboard, echo character to Console) x0024 [x04E0] PUTSP (Write “packed” string to Console) x0025 [xFD70] HALT (Turn off run latch in MCR) x0100 – x01FF Interrupt Vectors (Supports Hardware Interrupts) x0200 – x2FFF System Programs & Data (“Operating System”) x3000 – xFDFF User Programs Area xFE00 – xFFFF I/O Programming “Registers” (Mapped I/O Registers) xFE00 KBSR [15 {Ready}, 14 {Intr enable}] (Keyboard Status Register) xFE02 KBDR [7:0{ascii data}] (Keyboard Data Register) xFE04 DSR [15{Done}, 14{Intr enable}] (Display Status Register) xFE06 DDR [7:0{ascii data}] (Display Data Register xFFFE MCR [15{Run latch}] (Machine Control Register)

  3. Traps • Execute TRAP “vector” - Operating System Service Routines 2) Trap Vectors are at memory locations [0000:00FF] • Trap Vectors contain addresses of Trap Service Routines • (PC) is loaded into R7 • Address of Trap Service Routine loaded into PC • Service Routine Program executed • Trap service routine program ends with an RET ( (R7) loaded into PC)

  4. Subroutines JSR Instruction: JSR offset (11 bit) 0100 1 xxxxxxxxxxx [PC ] R7, JMP Offset Jump to Subroutine at offset from PC JSRR Instruction JSRR Rb 0100 0 00 xxx 000000 [PC ] R7, JMP [Reg] Jump to Subroutine at address in Rb Return RET 1100 000 111 000000 C1C0 [R7]  PC (JMP R7) Return to Instruction after Jump to Subroutine

  5. Subroutines • Execute JSR or JSRR - Call Subroutine or Method 2) Location of Subroutine is specified in the Instruction 3) [PC] stored in R7 4) Address from JSR or JSRR is loaded into PC • Subroutine is executed R0 likely contains passed parameter (or address) R5 may be used to return error message R0 likely contains return parameter (or address) 6) Subroutine program ends with an RET ( [R7] loaded into PC) How does this mechanism support recursion? It doesn’t! Implement a stack to accommodate recursion.

  6. Stack Push: Push ADD R6, R6, #-1 ; Decrement Stack Ptr STR R0, R6, #0 ; “Push” Data onto Stack Pop: Pop LDR R0, R6, #0 ; “Pop” Data off of Stack ADD R6, R6, #1 ; Increment Stack Ptr Which way does the Stack grow? Where does Stack Ptr (R6) point?

  7. Underflow Pop LD R1, Empty ; Compare Stack Ptr with x4000 ADD R2, R6, R1 BRz Underflow ; Underflow Error if nothing to Pop (Stack Empty) LDR R0, R6, #0 ; Pop Data ADD R6, R6, #1 ; Inc Stack Ptr AND R5, R5, #0 ; “Report” no error 0  R5 RET Underflow AND R5, R5, #0 ; “Report Error” 1  R5 ADD R5, R5, #1 RET Empty .FILL xC000 ; Empty  -x4000 (Beginning of Stack is 3FFF)

  8. Overflow Push LD R1, Full ; Compare Stack Ptr with Top of Stack (255 entries) ADD R2, R6, R1 BRz Overflow ; Overflow Error if no room to Push (Stack full) ADD R6, R6, #-1 ; Dec Stack Ptr STR R0, R6, #0 ; Push Data AND R5, R5, #0 ; “Report” no error 0  R5 RET Overflow AND R5, R5, #0 ; “Report Error” 1  R5 ADD R5, R5, #1 RET max .FILL xC100 ; Full  x3F00 (Top of Stack is xC0FF)

  9. Subroutine for Push & Pop ; Subroutines for carrying out the PUSH and POP functions. ; R6 is the stack pointer. R0 contains Data. R5 contains Error Report ; Stack: x3FFF (BASE) through x3FFB (MAX).; POP ST R2,Save2 ; are needed by POP. ST R1,Save1 LD R1,BASE ; BASE contains -x3FFF. ADD R1,R1,#-1 ; R1 contains -x4000. ADD R2,R6,R1 ; Compare stack pointer to x4000 BRz fail_exit ; Branch if stack is empty. LDR R0,R6,#0 ; The actual "pop." ADD R6,R6,#1 ; Adjust stack pointer BRnzp success_exit PUSH ST R2,Save2 ; Save registers that ST R1,Save1 ; are needed by PUSH. LD R1,MAX ; MAX contains -x3FFB ADD R2,R6,R1 ; Compare stack pointer to -x3FFB BRz fail_exit ; Branch if stack is full. ADD R6,R6,#-1 ; Adjust stack pointer STR R0,R6,#0 ; The actual "push" success_exit LD R1,Save1 ; Restore original LD R2,Save2 ; register values. AND R5,R5,#0 ; R5 <-- success. RET fail_exit LD R1,Save1 ; Restore original LD R2,Save2 ; register values. AND R5,R5,#0 ADD R5,R5,#1 ; R5 <-- failure. RET BASE .FILL xC001 ; BASE contains -x3FFF. MAX .FILL xC005 Save1 .FILL x0000 Save2 .FILL x0000 .END

  10. State of Program - Program Status Register PSR: PSR[15] – Privilege Bit PSR[10:8] – Priority Bits PSR[2:0] – Condition codes - N, Z, P

  11. Interrupts • Programmer Action: Enable Interrupts by setting “intr enable” bit in Device Status Reg • Enabling Mechanism for device: When device wants service, and its enable bit is set (The I/O device has the right to request service), and its priority is higher than the priority of the presently running program, and execution of an instruction is complete, then The processor initiates the interrupt • Process to service the interrupt: The Processor saves the “state” of the program (has to be able to return) The Processor goes into Privileged Mode (PSR bit 15 cleared) Priority level is set (established by the interrupting device) The (USP), (R6)  USP.saved register (UserStackPointer.saved) The (SSP.saved)  R6 (SupervisorStackPointer) The (PC) and the (PSR) are PUSHED onto the Supervisor Stack The contents of the other registers are not saved. Why? The CC’s are cleared • The Processor Loads the PC from the Interrupt vector (vectors in 0100:01FF) • Interrupt Service Routine is executed Ends with an RTI • The stored user PSR (POP into PSR), PC (POP into PC), (R6)SSP.saved, (USP.savedR6), and the next instruction fetched

  12. LC-3 Architecture - Figure C.8

  13. Interrupt Example Memory Maps SSP & PC

  14. TRAP x21 OUT Trap Vector Routine ; out.asm ; .ORIG x0430 ; System call starting address ST R1, SaveR1 ; R1 will be used to poll the DSR ; hardware ; ; Write the character ; TryWrite LDI R1, DSR ; Get status BRzp TryWrite ; Bit 15 on says display is ready WriteIt STI R0, DDR ; Write character ; ; return from trap ; Return LD R1, SaveR1 ; Restore registers RET ; Return from trap (JMP R7, actually) ; DSR .FILL xFE04 ; Address of display status register DDR .FILL xFE06 ; Address of display data register SaveR1 .BLKW 1 .END

  15. TRAP x22 PUTS Trap Vector Routine ; puts.asm ; This service routine writes a NULL-terminated string to the console. ; It services the PUTS service call (TRAP x22). ; Inputs: R0 is a pointer to the string to print. ; Context Information: R0, R1, and R3 are saved, and R7 is lost ; in the jump to this routine ; .ORIG x0450 ; Where this ISR resides ST R7, SaveR7 ; Save R7 for later return ST R0, SaveR0 ; Save other registers that ST R1, SaveR1 ; Are needed by this routine ST R3, SaveR3 ; ; ; Loop through each character in the array ; Loop LDR R1, R0, #0 ; Retrieve the character(s) BRz Return ; If it is 0, done L2 LDI R3,DSR BRzp L2 STI R1, DDR ; Write the character ADD R0, R0, #1 ; Increment pointer BRnzp Loop ; Do it all over again ; ; Return from the request for service call ; Return LD R3, SaveR3 LD R1, SaveR1 LD R0, SaveR0 LD R7, SaveR7 RET ; ; Register locations ; DSR .FILL xFE04 DDR .FILL xFE06 SaveR0 .FILL x0000 SaveR1 .FILL x0000 SaveR3 .FILL x0000 SaveR7 .FILL x0000 .END

  16. TRAP x25 HALT Trap Vector Routine ; halt.asm .ORIG xFD70 ; Where this routine resides ST R7, SaveR7 ST R1, SaveR1 ; R1: a temp for MC register ST R0, SaveR0 ; R0 is used as working space ; print message that machine is halting LD R0, ASCIINewLine TRAP x21 LEA R0, Message TRAP x22 LD R0, ASCIINewLine TRAP x21 ; ; clear bit 15 at xFFFE to stop the machine ; LDI R1, MCR ; Load MC register into R1 LD R0, MASK ; R0 = x7FFF AND R0, R1, R0 ; Mask to clear the top bit STI R0, MCR ; Store R0 into MC register ; ; return from HALT routine. ; (how can this routine return if the machine is halted above?) ; LD R1, SaveR1 ; Restore registers LD R0, SaveR0 LD R7, SaveR7 RET ; JMP R7, actually ; ; Some constants ; ASCIINewLine .FILL x000A SaveR0 .BLKW 1 SaveR1 .BLKW 1 SaveR7 .BLKW 1 Message .STRINGZ "Halting the machine." MCR .FILL xFFFE ; Address of MCR MASK .FILL x7FFF ; Mask to clear the top bit .END

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