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Front End Electronics for the NOvA Neutrino Detector John Oliver, Nathan Felt, Sarah Harder

Front End Electronics for the NOvA Neutrino Detector John Oliver, Nathan Felt, Sarah Harder. Long baseline neutrino experiment Fermilab (Chicago) to northern Minnesota (~800 km) ~15 kTon “Far” and smaller “Near” detectors. Electronics & DAQ Organization. L2 Manager – L. Mualem / UC

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Front End Electronics for the NOvA Neutrino Detector John Oliver, Nathan Felt, Sarah Harder

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  1. Front End Electronics for the NOvA Neutrino Detector John Oliver, Nathan Felt, Sarah Harder • Long baseline neutrino experiment • Fermilab (Chicago) to northern Minnesota (~800 km) • ~15 kTon “Far” and smaller “Near” detectors DoE Site Review / Harvard

  2. Electronics & DAQ Organization • L2 Manager – L. Mualem / UC • Electronic Project Engineer – J. Oliver / Harvard • Front End Boards (FEBs) • L3 Manager – J. Oliver • Elect Eng – N. Felt • Technician / designer – S. Harder • Test software – J. Boehm, S. Cavanaugh • DAQ, Timing – FNAL • ASIC development – T. Zimmerman, FNAL • Power Distribution & Slow Controls – UVa DoE Site Review / Harvard

  3. FEB DCM FEB DAQ & Timing GPS Receiver DCM FEB DCM Readout Hierarchy • ~12,000 Front End Boards (~ 1 FEB per 1.2 tons of NOvA detector) running synchronously • Each “hit”  timestamp synched to Global timing system + pulseheight • Global timing system with GPS receiver to correlate timing with NUMI beam spills • All data are buffered for ~ 10 seconds awaiting spill window information from NUMI beam line DoE Site Review / Harvard

  4. Power Distribution Data Concentrator DAQ Heirarchy – 64 FEBs to one “Data Concentrator FEBs Beam Beam Beam DAQ DoE Site Review / Harvard

  5. Front End Board (FEB) Architecture APD Module DAQ ASIC ADC FPGA TE Cooler Control • Thermoelectric cooler maintains – 15C at APD • ASIC integrates & shapes 32 signal channels from APD • Selectable risetime & falltime constants • ASIC’s 8:1 Multiplexers run @ 16 MHz to sample each channel at 500 ns/sample • ASIC’s four outputs are continuously digitized by quad ADC @ 16 Msps and sent to FPGA • ~ 12,000 FEBs in NOvA Far Detector DoE Site Review / Harvard

  6. Tf Tf Tf Tf 8 8 8 8 Tr Tr Tr Tr 8:1 Mux 8:1 Mux 8:1 Mux 8:1 Mux 32 ch NOvA ASIC (T. Zimmerman / FNAL) • 16 MHz multiplexers • 2 Msps per channel • Adjustable risetime & falltime • Status • Prototypes fabricated on TSMC 0.25u CMOS • Tested & work as per simulations • 2nd version now available to work at either Near or Far detectors. DoE Site Review / Harvard

  7. Sampled waveform g ( x ) g ( n ) 6 5 4 3 2 1 0 1 2 3 4 5 6 Signal Processing • Use multiple correlated pairs of samples centered on leading edge • Separate DSP filters in FPGA (firmware) for • Pulseheight • Timing • Triggering DoE Site Review / Harvard

  8. Summary & Status of NOvA FEB • Flexible architecture : Continuous digitization + DSP • 2 MSPS DSO on every channel (Far Detector): Local DSP filters in FPGA • Up to 8 MSPS for use in Near Detector (resolve event overlaps) • FEB Version 2.0 successfully tested in FY06-07 • FEB Version 3.0 • Works with NOvA ASIC V2.0 • Design completed Jan 08 • Project halted due to funding • Prototypes to be produced September 08 • Testing FY 09 • To be used on IPND – Schedule TBD • FEB V4.0 • May not be necessary if V3.0 meets all specs. (Minor changes to V3.0 V3.1) DoE Site Review / Harvard

  9. FEB V3.0 DoE Site Review / Harvard

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