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CPE 201 Digital Design

CPE 201 Digital Design. Lecture 23: Registers and Counters (2). Lecture Outline. Counters. Counters. Counter: a register that goes through a prescribed sequence of states Ripple counters: the flip-flop output triggers other flip-flops Synchronous counters count the clock. c. n. t.

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CPE 201 Digital Design

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  1. CPE 201Digital Design Lecture 23: Registers and Counters (2)

  2. Lecture Outline • Counters

  3. Counters • Counter: a register that goes through a prescribed sequence of states • Ripple counters: • the flip-flop output triggers other flip-flops • Synchronous counters • count the clock

  4. c n t 4-bit up-counter t c C 4 0 1 0000 1111 Counters • N-bit up-counter: N-bit register that can increment (add 1) to its own value on each clock cycle • 0000, 0001, 0010, 0011, ...., 1110, 1111, 0000 • Note how count “rolls over” from 1111 to 0000 • Terminal (last) count, tc, equals 1 during value just before rollover 1 0 0 0011 0100 0101 0001 0000 0010 1110 0001 ...

  5. Binary Ripple Counter Binary Count Sequence A3 A2 A1 A0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 … A0 is complemented with each count pulse A1 is complemented when A0 goes from 1 to 0 A2 is complemented when A1 goes from 1 to 0 A3 is complemented when A2 goes from 1 to 0

  6. Binary Ripple Counter • Use complementing flip-flops, with negative-edge transition • Connect the output of each flip-flop to the clock input of the next higher order flip-flop • Examples of complementing flip-flops • T flip-flop • D flip-flop: with the output complement connected to the input • JK flip-flop with both inputs connected to 1

  7. Examples of Binary Ripple Counters

  8. Binary Ripple Counter • Count-down counter: A binary counter with reverse count: starts from 15 and goes down • The least significant bit is complemented with every count pulse • Any other bit is complemented if the previous bit goes from 0 to 1 • We can use the same counter design (but with rising edge flip-flops) to make a count-down counter

  9. 4-bit Synchronous Binary Counters A flip-flop is complemented if all lower bits are 1. A3 A2 A1 A0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 ….

  10. Binary Counter with Parallel Load  This will provide appropriate JK inputs for all flip-flops, which enables counting Count = 1, Load =0 1 1 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0

  11. Binary Counter with Parallel Load  This will provide the external inputs at the JK inputs for all flip-flops, which enables loading Count = 0, Load =1 0 0 1 0 1 I0 I0 1 I0’ I0’ 1 I1 I1 0 1 I1’ I1’ 1 I2 I2 0 1 I2’ I2’ 1 I3 I3 0 1 I3’ I3’

  12. 4-bit Up-Down Binary Counters • In a down binary counter • The least significant bit is always complemented • A bit is complemented if all lower bits are 0 • Change an up counter to a down counter: • The AND gates should come from the complement outputs instead of the normal ones • Up = 1, Down =0: Circuit counts up since input comes from Normal output • Up = 0, Down =1: Circuit counts down since input comes from Complemented output

  13. mode c n t 2-bit up c ou n t er t c c1 c0 clk x y Counter Example: Mode in Above-Mirror Display • Recall above-mirror display example • Assumed component that incremented xy input each time button pressed: 00, 01, 10, 11, 00, 01, 10, 11, 00, ... • Can use 2-bit up-counter • Assumes mode=1 for just one clock cycle during each button press • Recall “Button press synchronizer” example

  14. 1 c n t 8-bit up-counter t c C osc 8 (256 Hz) p (unused) (1 Hz) Counter Example: 1 Hz Pulse Generator Using 256 Hz Oscillator • Suppose we have 256 Hz oscillator, but we want 1 Hz pulse • 1 Hz is 1 pulse per second – useful for keeping time • Design using 8-bit up-counter, use tc output as pulse • Counts from 0 to 255 (256 counts), so pulses tc every 256 cycles

  15. 3-bit u p - c ou n t er c n t 1 clk t c c2 c1 c0 (1 H z) 0 0 0 0 0 1 1 0 0 unused x 3 8 d c d i2 i1 i0 d7 d6 d5 d4 d3 d2 d1 d0 Counter Example: Light Sequencer • Illuminate 8 lights from right to left, one at a time, one per second • Use 3-bit up-counter to count from 0 to 7 • Use 3x8 decoder to illuminate appropriate light • Note: Used 3-bit counter with 3x8 decoder • NOT an 8-bit counter lig h ts

  16. 4-bit up-counter c n t ld 4-bit register 4 4 +1 4 4 t c C Counters • Alternative internal design • Register, incrementer, and N-input AND gate to detect terminal count

  17. a3 a2 a1 a0 1 a3 a2 a1 a0 a b a b a b a b +1 HA HA HA HA c o s3 s2 s1 s0 c o s c o s c o s c o s c o s3 s2 s1 s0 ( b ) ( a ) carries: 0 1 1 0 0 1 1 unused + 1 0 0 1 0 0 Incrementer • Could use carry-ripple adder with B input set to 00...001 • But when adding 00...001 to another number, the leading 0’s obviously don’t need to be considered - so just two bits being added per column • Use half-adders (add two bits) rather than full-adders (add three bits)

  18. 4-bit down-counter c n t ld 4-bit register 4 4 –1 4 t c C 4 Down-Counter • 4-bit down-counter • 1111, 1110, 1101, 1100, …, 0011, 0010, 0001, 0000, 1111, … • Need decrementer (-1) • design similar to incrementer • Terminal count is 0000 • Use NOR gate to detect

  19. 4-bit up/down counter dir x 1 4-bit 2 1 0 4 clr clr c n t ld 4-bit register 4 4 4 4 –1 +1 4 4 4 x 1 2 1 0 t c C Up/Down-Counter • Can count either up or down • Includes both incrementer and decrementer • Use dir input to select, using 2x1: dir=0 means up • Likewise, dir selects appropriate terminal count value

  20. L 4 ld x 1 4-bit 2 1 0 4 c n t ld 4-bit register 4 4 +1 4 t c C Counter with Parallel Load • Up-counter that can be loaded with external value • Designed using 2x1 mux – ld input selects incremented value or external value • Load the internal register when loading external value or when counting

  21. 4 ld L 1 c n t t c C clk 4 Example with Down Counter 1000 • Useful to create pulses at specific multiples of clock • Not just at N-bit counter’s natural wrap-around of 2N • E.g.: Pulse every 9 clock cycles • Use 4-bit down-counter with parallel load • Set parallel load input to 8 (1000) • Use terminal count to reload • When count reaches 0, next cycle loads 8 • Why load 8 and not 9? • Because 0 is included in count sequence: 8, 7, 6, 5, 4, 3, 2, 1, 0  9 counts 4-bit down-counter

  22. Happy 0 New d0 8 Year 59 c0 i0 L d1 c1 i1 1 d2 c2 i2 2 ld d3 3 c3 i3 reset c4 i4 c5 i5 d58 c6 d59 c n t c7 countdown d60 58 d61 59 8-bit clk d62 fireworks down- (1 Hz) 6x64 t c d63 counter dcd Counter Example: New Year’s Eve Countdown Display • Count from 59 down to 0 in binary using microprocessor • Can use 8-bit (or 7- or 6-bit) down-counter instead, initially loaded with 59

  23. clr c n t 1 6-bit up counter osc t c C (60 Hz) p (1 Hz) Counter Example: 1 Hz Pulse Generator from 60 Hz Clock • Have 60 Hz signal • Need device to convert that to 1 Hz signal to count seconds • Use clear input • Use 6-bit up-counter • Can count from 0 to 63 • Create simple logic to detect 59 (for 60 counts) • Use to clear the counter back to 0 (or to load 0)

  24. Readings • Chapter 6 • Sections 6.3 – 6.5

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