CSE243: Introduction to Computer Architecture and Hardware/Software Interface

1. CSE243: Introduction to Computer Architecture and Hardware/Software Interface

2. Basic concepts • Speed of execution of programs can be improved in two ways: • Faster circuit technology to build the processor and the memory. • Arrange the hardware so that a number of operations can be performed simultaneously. The number of operations performed per second is increased although the elapsed time needed to perform any one operation is not changed. • Pipelining is an effective way of organizing concurrent activity in a computer system to improve the speed of execution of programs.

3. T ime 1 2 3 F E F E F E 1 1 2 2 3 3 Basic concepts (contd..) • Processor executes a program by fetching and executing instructions one after the • other. • This is known as sequential execution. • If Fi refers to the fetch step, and Ei refers to the execution step of instruction Ii, • then sequential execution looks like: What if the execution of one instruction is overlapped with the fetching of the next one?

4. Interstage buffer B1 Instruction Ex ecution fetch unit unit Basic concepts (contd..) • Computer has two separate hardware units, one for fetching instructions and one • for executing instructions. • Instruction is fetched by instruction fetch unit and deposited in an intermediate • buffer B1. • Buffer enables the instruction execution unit to execute the instruction while the • fetch unit is fetching the next instruction. • Results of the execution are deposited in the destination location specified by the • instruction.

5. T ime Clock cycle 1 2 3 4 Instruction I F E 1 1 1 I F E 2 2 2 I F E 3 3 3 Basic concepts (contd..) • Computer is controlled by a clock whose period is such that the fetch and execute • steps of any instruction can be completed in one clock cycle. • First clock cycle: • - Fetch unit fetches an instruction I1 (F1) and stores it in B1. • Second clock cycle: • - Fetch unit fetches an instruction I2 (F2) , and execution unit executes instruction I1 (E1). • Third clock cycle: • - Fetch unit fetches an instruction I3 (F3), and execution unit executes instruction I2 (E2). • Fourth clock cycle: • - Execution unit executes instruction I3 (E3).

6. Basic concepts (contd..) • In each clock cycle, the fetch unit fetches the next instruction, while the execution unit executes the current instruction stored in the interstage buffer. • Fetch and the execute units can be kept busy all the time. • If this pattern of fetch and execute can be sustained for a long time, the completion rate of instruction execution will be twice that achievable by the sequential operation. • Fetch and execute units constitute a two-stage pipeline. • Each stage performs one step in processing of an instruction. • Interstage storage buffer holds the information that needs to be passed from the fetch stage to execute stage. • New information gets loaded into the buffer every clock cycle.

7. Basic concepts (contd..) • Suppose the processing of an instruction is divided into four steps: • F Fetch: Read the instruction from the memory. • D Decode: Decode the instruction and fetch the source operands. • E Execute: Perform the operation specified by the instruction. • W Write: Store the result in the destination location. • There are four distinct hardware units, for each one of the steps. • Information is passed from one unit to the next through an interstage buffer. • Three interstage buffers connecting four units. • As an instruction progresses through the pipeline, the information needed by the • downstream units must be passed along. Interstage b uf fers D : Decode F : Fetch instruction E: Ex ecute W : Write instruction and fetch operation results operands B1 B2 B3

8. T ime Clock cycle 1 2 3 4 5 6 7 Instruction I F D E W 1 1 1 1 1 I F D E W 2 2 2 2 2 I F D E W 3 3 3 3 3 I F D E W 4 4 4 4 4 Basic concepts (contd..) Clock cycle 1: F1 Clock cycle 2: D1, F2 Clock cycle 3: E1, D2, F3 Clock cycle 4: W1, E2, D3, F4 Clock cycle 5: W2, E3, D4 Clock cycle 6: W3, E3, D4 Clock cycle 7: W4

9. T ime Clock cycle 1 2 3 4 5 6 7 Instruction I F D E W 1 1 1 1 1 I F D E W 2 2 2 2 2 I F D E W 3 3 3 3 3 I F D E W 4 4 4 4 4 Basic concepts (contd..) During clock cycle #4: • Buffer B1 holds instruction I3, which is being decoded by the instruction-decoding • unit. Instruction I3 was fetched in cycle 3. • Buffer B2 holds the source and destination operands for instruction I2. It also holds • the information needed for the Write step (W2) of instruction I2. This information • will be passed to the stage W in the following clock cycle. • Buffer B1 holds the results produced by the execution unit and the destination • information for instruction I1.

10. Role of cache memory • Each stage in the pipeline is expected to complete its operation in one clock cycle: • Clock period should be sufficient to complete the longest task. • Units which complete the tasks early remain idle for the remaining clock period. • Tasks being performed in different stages should require about the same amount of time for pipelining to be effective. • If instructions are to be fetched from the main memory, the instruction fetch stage would take as much as ten times greater than the other stage operations inside the processor. • However, if instructions are to be fetched from the cache memory which is on the processor chip, the time required to fetch the instruction would be more or less similar to the time required for other basic operations.

11. Pipeline performance • Potential increase in performance achieved by using pipelining is proportional to the number of pipeline stages. • For example, if the number of pipeline stages is 4, then the rate of instruction processing is 4 times that of sequential execution of instructions. • Pipelining does not cause a single instruction to be executed faster, it is the throughput that increases. • This rate can be achieved only if the pipelined operation can be sustained without interruption through program instruction. • If a pipelined operation cannot be sustained without interruption, the pipeline is said to “stall”. • A condition that causes the pipeline to stall is called a “hazard”.

12. T ime Clock cycle 1 2 3 4 5 6 7 Instruction I F D E W 1 1 1 1 1 I F D E W 2 2 2 2 2 I F D E W 3 3 3 3 3 I F D E W 4 4 4 4 4 Data hazard • Execution of the instruction occurs in the E stage of the pipeline. • Execution of most arithmetic and logic operations would take only one clock cycle. • However, some operations such as division would take more time to complete. • For example, the operation specified in instruction I2 takes three cycles to complete • from cycle 4 to cycle 6.

13. T ime Clock cycle 1 2 3 4 5 6 7 Instruction I F D E W 1 1 1 1 1 I F D E W 2 2 2 2 2 I F D E W 3 3 3 3 3 I F D E W 4 4 4 4 4 Data hazard (contd..) • Cycles 5 and 6, the Write stage is idle, because it has no data to work with. • Information in buffer B2 must be retained till the execution of the instruction I2 is • complete. • Stage 2, and by extension stage 1 cannot accept new instructions because the • information in B1 cannot be overwritten. • Steps D6 and F5 must be postponed. • A data hazard is a condition in which either the source or the destination operand is • not available at the time expected in the pipeline.

14. T ime Clock c ycle 1 2 3 4 5 6 7 8 9 Instruction I F D E W 1 1 1 1 1 I F D E W 2 2 2 2 2 I F D E W 3 3 3 3 3 Control or instruction hazard • Pipeline may be stalled because an instruction is not available at the expected time. • For example, while fetching an instruction a cache miss may occur, and hence the • instruction may have to be fetched from the main memory. • Fetching the instruction from the main memory takes much longer than fetching the • instruction from the cache. • Thus, the fetch cycle of the instruction cannot be completed in one cycle. • For example, the fetching of instruction I2 results in a cache miss. • Thus, F2 takes 4 clock cycles instead of 1.

15. T ime Clock c ycle 1 2 3 4 5 6 7 8 9 Stage F: Fetch F F F F F F 1 2 2 2 2 3 D: Decode D idle idle idle D D 1 2 3 E: Execute E idle idle idle E E 1 2 3 W: Write W idle idle idle W W 1 2 3 Control or instruction hazard (contd..) • Fetch operation for instruction I2 results in a cache miss, and the instruction fetch • unit must fetch this instruction from the main memory. • Suppose fetching instruction I2 from the main memory takes 4 clock cycles. • Instruction I2 will be available in buffer B1 at the end of clock cycle 5. • The pipeline resumes its normal operation at this point. • Decode unit is idle in cycles 3 through 5. • Execute unit is idle in cycles 4 through 6. • Write unit is idle in cycles 5 through 7. • Such idle periods are called as stalls or bubbles. • Once created in one of the pipeline stages, a bubble moves downstream unit it • reaches the last unit.

16. Structural hazard • Two instructions require the use of a hardware resource at the same time. • Most common case is in access to the memory: • One instruction needs to access the memory as part of the Execute or Write stage. • Other instruction is being fetched. • If instructions and data reside in the same cache unit, only one instruction can proceed and the other is delayed. • Many processors have separate data and instruction caches to avoid this delay. • In general, structural hazards can be avoided by providing sufficient resources on the processor chip.

17. Structural hazard (contd..) Clock c ycle 1 2 3 4 5 6 7 Instruction I F D E W 1 1 1 1 1 (Load X(R1),R2 I F D E M W 2 2 2 2 2 2 I F D E W 3 3 3 3 3 I F D E 4 4 4 4 I F D 5 5 5 • Memory address X+R1 is computed in step E2 in cycle 4, memory access takes place • in cycle 5, operand read from the memory is written into register R2 in cycle 6. • Execution of instruction I2 takes two clock cycles 4 and 5. • In cycle 6, both instructions I2 and I3 require access to register file. • Pipeline is stalled because the register file cannot handle two operations at once.

18. Pipelining and performance • Pipelining does not cause an individual instruction to be executed faster, rather, it increases the throughput. • Throughput is defined as the rate at which instruction execution is completed. • When a hazard occurs, one of the stages in the pipeline cannot complete its operation in one clock cycle. • The pipeline stalls causing a degradation in performance. • Performance level of one instruction completion in each clock cycle is the upper limit for the throughput that can be achieved in a pipelined processor.

19. Data hazards • Data hazard is a situation in which the pipeline is stalled because the data to be • operated on are delayed. • Consider two instructions: • I1: A = 3 + A • I2: B = 4 x A • If A = 5, and I1 and I2 are executed sequentially, B=32. • In a pipelined processor, the execution of I2 can begin before the execution of I1. • The value of A used in the execution of I2 will be the original value of 5 leading to • an incorrect result. • Thus, instructions I1 and I2 depend on each other, because the data used by I2 • depends on the results generated by I1. • Results obtained using sequential execution of instructions should be the same as • the results obtained from pipelined execution. • When two instructions depend on each other, they must be performed in the correct • order.

20. Clock c ycle 1 2 3 4 5 6 7 8 9 Data hazards (contd..) Instruction Mul R2, R3, R4 I F D E W 1 1 1 1 1 Add R5,R4,R6 F D D E W I 2 2 2A 2 2 2 F D E W I 3 3 3 3 3 I F D E W 4 4 4 4 4 • Mul instruction places the results of the multiply operation in register R4 at the end • of clock cycle 4. • Register R4 is used as a source operand in the Add instruction. Hence the Decode • Unit decoding the Add instruction cannot proceed until the Write step of the first • instruction is complete. • Data dependency arises because the destination of one instruction is used as a source • in the next instruction.

21. Operand forwarding • Data hazard occurs because the destination of one instruction is used as the source • in the next instruction. • Hence, instruction I2 has to wait for the data to be written in the register file by the • Write stage at the end of step W1. • However, these data are available at the output of the ALU once the Execute stage • completes step E1. • Delay can be reduced or even eliminated if the result of instruction I1 can be • forwarded directly for use in step E2. • This is called “operand forwarding”.

22. Source 1 Source 2 SRC1 SRC2 Re gister file ALU RSL T Destination Operand forwarding (contd..) • Similar to the three-bus organization. • Registers SRC1, SRC2 and RSLT have • been added. • SRC1, SRC2 and RSLT are interstage • buffers for pipelined operation. • SRC1 and SRC2 are part of buffer B2. • RSLT is part of buffer B3. • Data forwarding mechanism is shown by • the two red lines. • Two multiplexers connected at the inputs • to the ALU allow the data on the destination • bus to be selected instead of the contents of • SRC1 and SRC2 register.

23. Source 1 Source 2 SRC1 SRC2 Re gister file ALU RSL T Destination Operand forwarding (contd..) I1: Mul R2, R3, R4 I2: Add R5, R4, R6 Clock cycle 3: - Instruction I2 is decoded, and a data dependency is detected. - Operand not involved in the dependency, register R5 is loaded in register SRC1. Clock cycle 4: - Product produced by I1 is available in register RSLT. - The forwarding connection allows the result to be used in step E2. Instruction I2 proceeds without interruption.

24. Handling data dependency in software • Data dependency may be detected by the hardware while decoding the instruction: • Control hardware may delay by an appropriate number of clock cycles reading of a register till its contents become available. The pipeline stalls for that many number of clock cycles. • Detecting data dependencies and handling them can also be accomplished in software. • Compiler can introduce the necessary delay by introducing an appropriate number of NOP instructions. For example, if a two-cycle delay is needed between two instructions then two NOP instructions can be introduced between the two instructions. I1: Mul R2, R3, R4 NOP NOP I2: Add R5, R4, R6

25. Side effects • Data dependencies are explicit easy to detect if a register specified as the destination in one instruction is used as a source in the subsequent instruction. • However, some instructions also modify registers that are not specified as the destination. • For example, in the autoincrement and autodecrement addressing mode, the source register is modified as well. • When a location other than the one explicitly specified in the instruction as a destination location is affected, the instruction is said to have a “side effect”. • Another example of a side effect is condition code flags which implicitly record the results of the previous instruction, and these results may be used in the subsequent instruction.

26. Side effects (contd..) I1: Add R3, R4 I2: AddWithCarry R2, R4 Instruction I1 sets the carry flag and instruction I2 uses the carry flag leading to an implicit dependency between the two instructions. • Instructions with side effects can lead to multiple data dependencies. • Results in a significant increase in the complexity of hardware or software needed • to handle the dependencies. • Side effects should be kept to a minimum in instruction sets designed for execution • on pipelined hardware.

27. Instruction hazards • Instruction fetch units fetch instructions and supply the execution units with a steady stream of instructions. • If the stream is interrupted then the pipeline stalls. • Stream of instructions may be interrupted because of a cache miss or a branch instruction.

28. Instruction hazards (contd..) Consider a two-stage pipeline, first stage is the instruction fetch stage and the second stage is the instruction execute stage. Instructions I1, I2 and I3 are stored at successive memory locations. I2 is a branch instruction with branch target as instruction Ik. I2 is an unconditional branch instruction. Clock cycle 3: - Fetch unit is fetching instruction I3. - Execute unit is decoding I2 and computing the branch target address. Clock cycle 4: - Processor must discard I3 which has been incorrectly fetched and fetch Ik. - Execution unit is idle, and the pipeline stalls for one clock cycle.

29. T ime Clock c ycle 1 2 3 4 5 6 Instruction I F E 1 1 1 Ex ecution unit idle I (Branch) F E 2 2 2 I F X 3 3 I F E k k k I F E k +1 k+ 1 k+ 1 Instruction hazards (contd..) • Pipeline stalls for one clock cycle. • Time lost as a result of a branch instruction is called as branch penalty. • Branch penalty is one clock cycle.

30. T ime Clock c ycle 1 2 3 4 5 6 7 8 F D E W I 1 1 1 1 1 F I (Branch) D E 2 2 2 2 F D X I 3 3 3 F X I 4 4 F D E W I k k k k k F D E I k+ 1 k+ 1 k+ 1 k+ 1 Instruction hazards (contd..) Branch penalty depends on the length of the pipeline, may be higher for a longer pipeline. For a four-stage pipeline: - Branch target address is computed in stage E2. - Instructions I3 and I4 have to be discarded. - Execution unit is idle for 2 clock cycles. - Branch penalty is 2 clock cycles.

31. T ime Clock c ycle 1 2 3 4 5 6 7 F D E W I 1 1 1 1 1 F D I (Branch) 2 2 2 F X I 3 3 F D E W I k k k k k F D E I k+ 1 k+ 1 k+ 1 k+ 1 Instruction hazards (contd..) • Branch penalty can be reduced by computing the branch target address earlier in the • pipeline. • Instruction fetch unit has special hardware to identify a branch instruction after the • instruction is fetched. • Branch target address can be computed in the Decode stage (D2), rather than in the • Execute stage (E2). • Branch penalty is only one clock cycle.

32. Instruction queue F : Fetch instruction Instruction fetch unit D : Dispatch/ E : Ex ecute W : Write Decode instruction results unit Instruction hazards (contd..) Queue can hold several instructions Fetch unit fetches instructions before they are needed & stores them in a queue Dispatch unit takes instructions from the front of the queue and dispatches them to the Execution unit. Dispatch unit also decodes the instruction.

33. Instruction hazards (contd..) • Fetch unit must have sufficient decoding and processing capability to recognize and execute branch instructions. • Pipeline stalls because of a data hazard: • Dispatch unit cannot issue instructions from the queue. • Fetch unit continues to fetch instructions and add them to the queue. • Delay in fetching because of a cache miss or a branch: • Dispatch unit continues to dispatch instructions from the instruction queue.

34. Instruction hazards (contd..) Clock c ycle 1 2 3 4 5 6 7 8 9 10 Queue length 1 1 1 1 2 3 2 1 1 1 • Initial length of the queue is 1. • Fetch adds 1 to the queue, dispatch • reduces the length by 1. • Queue length remains the same • for first 4 clock cycles. • I1 stalls the pipeline for 2 cycles. • Queue has space, so the fetch unit • continues and queue length rises • to 3 in clock cycle 6. F D E E E W I 1 1 1 1 1 1 1 F D E W I 2 2 2 2 2 F D E W I 3 3 3 3 3 F D E W I 4 4 4 4 4 F D I (Branch) 5 5 5 • I5 is a branch instruction with • target instruction Ik. • Ik is fetched in cycle 7, and I6 • is discarded. • However, this does not stall the • pipeline, since I4 is dispatched. F X I 6 6 F D E W I k k k k k F D E I k+ 1 k+ 1 k+ 1 k+ 1 I2, I3, I4 and Ik are executed in successive clock cycles. Fetch unit computes the branch address concurrently with the execution of other instructions. This is called as branch folding.

35. Instruction hazards (contd..) • Branch folding can occur if there is at least one instruction available in the queue other than the branch instruction. • Queue should ideally be full most of the time. • Increasing the rate at which the fetch unit reads instructions from the cache. • Most processors allow more than one instruction to be fetched from the cache in one clock cycle. • Fetch unit must replenish the queue quickly after a branch has occurred. • Instruction queue also mitigates the impact of cache misses: • In the event of a cache miss, the dispatch unit continues to send instructions to the execution unit as long as the queue is full. • In the meantime, the desired cache block is read. • If the queue does not become empty, cache miss has no effect on the rate of instruction execution.

36. Conditional branches and branch prediction • Conditional branch instructions depend on the result of a preceding instruction. • Decision on whether to branch cannot be made until the execution of the preceding instruction is complete. • Branch instructions represent 20% of the dynamic instruction count of most programs. • Dynamic instruction count takes into consideration that some instructions are executed repeatedly. • Branch instructions may incur branch penalty reducing the performance gains expected from pipelining. • Several techniques to mitigate the negative impact of branch penalty on performance.

37. T ime Clock c ycle 1 2 3 4 5 6 7 8 F D E W I 1 1 1 1 1 F I (Branch) D E 2 2 2 2 F D X I 3 3 3 F X I 4 4 F D E W I k k k k k F D E I k+ 1 k+ 1 k+ 1 k+ 1 Delayed branch • Branch target address is computed in stage E2. • Instructions I3 and I4 have to be discarded. • Location following a branch instruction is called a branch delay slot. • There may be more than one branch delay slot depending on the time it takes to • determine whether the instruction is a branch instruction. • In this case, there are two branch delay slots. • The instructions in the delay slot are always fetched and at least partially executed • before the branch decision is made and the branch address is computed.

38. Delayed branch (contd..) • Delayed branching can minimize the penalty incurred as a result of conditional branch instructions. • Since the instructions in the delay slots are always fetched and partially executed, it is better to arrange for them to be fully executed whether or not branch is taken. • If we are able to place useful instructions in these slots, then they will always be executed whether or not the branch is taken. • If we cannot place useful instructions in the branch delay slots, then we can fill these slots with NOP instructions.

39. LOOP Shift_left R1 Decrement R2 Branch=0 LOOP NEXT Add R1,R3 (a) Original program loop LOOP Decrement R2 Branch=0 LOOP Shift_left R1 NEXT Add R1,R3 Delayed branch (contd..) Register R2 is used as a counter to determine how many times R1 is to be shifted. Processor has a two stage pipeline or one delay slot. Instructions can be reordered so that the shift left instruction appears in the delay slot. Shift left instruction is always executed whether the branch condition is true or false. (b) Reordered instructions

40. T ime Clock c ycle 1 2 3 4 5 6 7 8 Instruction Decrement F E Branch F E Shift (delay slot) F E Decrement (Branch tak en) F E Branch F E Shift (delay slot) F E Add (Branch not tak en) F E Delayed branch (contd..) Shift instruction is executed when the branch is taken. Shift instruction is executed when the branch is not taken.

41. Delayed branch (contd..) • Logically, the program is executed as if the branch instruction were placed after the shift instruction. • Branching takes place one instruction later than where the branch instruction appears in the instruction sequence (with reference to reordered instructions). • Hence, this technique is termed as “delayed branch”. • Delayed branch requires reordering as many instructions as the number of delay slots. • Usually possible to reorganize one instruction to fill one delay slot. • Difficult to reorganize two or more instructions to fill two or more delay slots.

42. Branch prediction • To reduce the branch penalty associated with conditional branches, we can predict whether the branch will be taken. • Simplest form of branch prediction: • Assume that the branch will not take place. • Continue to fetch instructions in sequential execution order. • Until the branch condition is evaluated, instruction execution along the predicted path must be done on a speculative basis. • “Speculative execution” implies that the processor is executing instructions before it is certain that they are in the correct sequence. • Processor registers and memory locations should not be updated unless the sequence is confirmed. • If the branch prediction turns out to be wrong, then instructions that were executed on a speculative basis and their data must be purged. • Correct sequence of instructions must be fetched and executed.

43. T ime 1 2 3 4 5 6 Clock cycle Instruction I (Compare) F D E W 1 1 1 1 1 I (Branch>0) F D /P E 2 2 2 2 2 I F D X 3 3 3 I F X 4 4 I F D k k k Branch prediction (contd..) • I1 is a compare instruction and I2 • is a branch instruction. • Branch prediction takes place in cycle • 3 when I2 is being decoded. • I3 is being fetched at that time. • Fetch unit predicts that the branch will • not be taken and continues to fetch I4 • in cycle 4 when I3 is being decoded. • Results of I1 are available in cycle 3. • Fetch unit evaluates branch condition in cycle 4. • If the branch prediction is incorrect, the fetch unit realizes at this point. • I3 and I4 are discarded and Ik is fetched from the branch target address.

44. Branch prediction (contd..) • If branch outcomes were random, then the simple approach of always assuming that the branch would not be taken would be correct 50% of the time. • However, branch outcomes are not random and it may be possible to determine a priori whether a branch will be taken or not depending on the expected program behavior. • For example, a branch instruction at the end of the loop causes a branch to the start of the loop for every pass through the loop except the last one. Better performance can be achieved if this branch is always predicted as taken. • A branch instruction at the beginning of the loop causes the branch to be not taken most of the time. Better performance can be achieved if this branch is always predicted as not taken.

45. Branch prediction (contd..) • Which way to predict the result of the branch instruction (taken or not taken) may be made in the hardware, depending on whether the target address of the branch instruction is lower or higher than the address of the branch instruction. • If the target address is lower, then the branch is predicted as taken. • If the target address is higher, then the branch is predicted as not taken. • Branch prediction can also be handled by the compiler. • Complier can set the branch prediction bit to 0 or 1 to indicate the desired behavior. • Instruction fetch unit checks the branch prediction bit to predict whether the branch will be taken.

46. Branch prediction (contd..) • Branch prediction decision is the same every time an instruction is executed. • This is “static branch prediction”. • Branch prediction decision may change depending on the execution history. • This is “dynamic branch prediction”.

47. Branch prediction (contd..) • Branch prediction algorithms should minimize the probability of making a wrong branch prediction decision. • In dynamic branch prediction the processor hardware assesses the likelihood of a given branch being taken by keeping track of branch decisions every time that instruction is executed. • Simplest form of execution history used in predicting the outcome of a given branch instruction is the result of the most recent execution of that instruction. • Processor assumes that the next time the instruction is executed, the result is likely to be the same. • For example, if the branch was taken the last time the instruction was executed, then the branch is likely to be taken this time as well.

48. Branch taken (BT) BNT LNT BT LT Branch not taken (BNT) Branch prediction (contd..) Branch prediction algorithm may be described as a two-state machine with 2 states: LT : Branch is likely to be taken LNT: Branch is likely not to be taken Initial state of the machine be LNT When the branch instruction is executed, and if the branch is taken, the machine moves to state LT. If the branch is not taken, it remains in state LNT. When the same branch instruction is executed the next time, the branch is predicted as taken if the state of the machine is LT, else it is predicted as not taken.

49. Branch prediction (contd..) • Requires only one bit of history information for each branch instruction. • Works well inside loops: • Once a loop is entered, the branch instruction that controls the looping will always yield the same result until the last pass. • In the last pass, the branch prediction will turn out to be incorrect. • The branch history state machine will be changed to the opposite state. • However, if the same loop is entered the next time, and there is more than one pass, the branch prediction machine will lead to wrong branch prediction. • Better performance may be achieved by keeping more execution history.

50. LT ST Branch prediction (contd..) BT • Initial state of the algorithm is LNT. • After the branch instruction is executed, if • the branch is taken, the state is changed to ST • For a branch instruction, the fetch unit predicts • that the branch will be taken if the state is ST • or LT, else it predicts that the branch will not • be taken. • In state SNT: • - The prediction is that the branch is not taken. • - If the branch is actually taken, the state • changes to LNT. • - Next time the branch is encountered, the • prediction again is that it is not taken. • - If the prediction is wrong the second time, • the state changes to ST. • - After that, the branch is predicted as taken. LNT SNT BNT BNT BNT BT BT BT BNT ST : Strong likely to be taken LT : Likely to be taken LNT : Likely not to be taken SNT : Strong likely not to be taken