Module 1 Overview: Introduction to Computer Architecture and Organization

1. Module 1 Overview: Introduction to Computer Architecture and Organization

2. Architecture & Organization 1 • Architecture is those attributes visible to the programmer • Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques. • e.g. Is there a multiply instruction? • Organization is how architecture features are implemented • Control signals, interfaces, memory technology. • e.g. Is there a hardware multiply unit or is it done by repeated addition?

3. Architecture & Organization 2 • All Intel x86 family share the same basic architecture • The IBM System/370 family share the same basic architecture • This gives code compatibility • At least backwards • Organization differs between different versions

4. Structure & Function • Structure is the way in which components relate to each other • Function is the operation of individual components as part of the structure

5. Function • All basic computer functions are: • Data processing–process data in variety of forms and requirements • Data storage–short and long term data storage for retrieval and update • Data movement–move data between computer and outside world. Devices that serve as source and destination of data–the process is known as I/O • Control–control of process, move and store data using instruction.

6. Functional View

7. Operations (b) Data storage device operation – read and write Operations (a) Data movement device operation

8. Operation (d)Processing from storage to I/O Operation (c) Processing from/to storage

9. Structure - Top Level - 1 Computer Peripherals Central Processing Unit Main Memory Computer Systems Interconnection Input Output Communication lines

10. Structure - Top Level - 2 • Central Processing Unit (CPU) – controls operation of the computer and performs data processing functions • Main memory – stores data • I/O – moves data between computer and external environment • System interconnection – provides communication between CPU, main memory and I/O

11. Structure - The CPU - 1 CPU Arithmetic and Login Unit Computer Registers I/O System Bus CPU Internal CPU Interconnection Memory Control Unit

12. Structure - The CPU - 2 • Control unit (CU)–control the operation of CPU • Arithmetic and logic unit (ALU)-performs data processing functions • Registers-provides internal storage to the CPU • CPU Interconnection-provides communication between control unit (CU), ALU and registers

13. Structure - The Control Unit Control Unit CPU Sequencing Login ALU Control Unit Internal Bus Control Unit Registers and Decoders Registers Control Memory Implementation of control unit – micro programmed implementation

14. Module 1 Overview: Von Neumann Machine and Computer Evolution

15. First Generation – Vacuum TubesENIAC - background • Electronic Numerical Integrator And Computer • Eckert and Mauchly • University of Pennsylvania • Trajectory tables for weapons (range and trajectory) • Started 1943 • Finished 1946 • Too late for war effort, but used determine the feasibility of hydrogen bomb • Used until 1955

16. ENIAC - diagram

17. ENIAC - details • Decimal (not binary) • 20 accumulators of 10 digits • Programmed manually by switches • 18,000 vacuum tubes • 30 tons • 15,000 square feet • 140 kW power consumption • 5,000 additions per second

18. Von Neumann Machine/Turing • Stored Program concept • Main memory storing programs and data- That could be changed and programming will become easier • ALU operating on binary data • Control unit interpreting instructions from memory and executing • Input and output (I/O) equipment operated by control unit • Princeton Institute for Advanced Studies • IAS computer • Completed 1952

19. Structure of von Neumann machine

20. Von Neumann Architecture • Data and instruction are stored in a single read-write memory • The contents of this memory is addressable by location • Execution occurs in a sequential fashion from one instruction to the next

21. IAS – details-1 • 1000 x 40 bit words • Binary number – number word • 2 x 20 bit instructions – instruction word1

22. IAS – details-2 • Set of registers (storage in CPU) • Memory Buffer Register–contains word to be stored in memory or sent to I/O unit, receive a word from memory of from I/O unit • Memory Address Register–specify the address in memory for MBR • Instruction Register-contains opcode • Instruction Buffer Register-temporary storage for instruction • Program Counter-contains next instruction to be fetched from memory • Accumulator and Multiplier Quotient-temporary storage for operands and result of ALU operations

23. Structure of IAS – detail-3 Control unit– fetches instructions from memory and executes them one by one

24. Commercial Computers • 1947 - Eckert-Mauchly Computer Corporation-manufacture computer commercially • UNIVAC I (Universal Automatic Computer)-first commercial computer • US Bureau of Census 1950 calculations • Became part of Sperry-Rand Corporation • Late 1950s - UNIVAC II • Faster • More memory

25. IBM • Punched-card processing equipment • 1953 - the 701 • IBM’s first stored program computer • Scientific calculations • 1955 - the 702 • Business applications • Lead to 700/7000 series

26. Second Generation: Transistors • Replaced vacuum tubes • Smaller • Cheaper • Less heat dissipation • Solid State device • Made from Silicon (Sand) • Invented 1947 at Bell Labs • William Shockley et al.

27. Transistor Based Computers • Second generation machines • More complex arithmetic and logic unit(ALU)and control unit(CU) • Use of high level programming languages • NCR & RCA produced small transistor machines • IBM 7000 • DEC - 1957 • Produced PDP-1

28. Transistors Based Computers

29. The Third Generation: Integrated CircuitsMicroelectronics • Literally - “small electronics” • A computer is made up of gates, memory cells and interconnections • Data storage-provided by memory cells • Data processing-provided by gates • Data movement-the paths between components that are used to move data • Control-the paths between components that carry control singnals • These can be manufactured on a semiconductor • e.g. silicon wafer

30. Integrated Circuits Early integrated circuits- know as small scale integration (SSI)

31. Moore’s Law • Increased density of components on chip-refer chart • Gordon Moore – co-founder of Intel • Number of transistors on a chip will double every year-refer chart • Since 1970’s development has slowed a little • Number of transistors doubles every 18 months • Cost of a chip has remained almost unchanged • Higher packing density means shorter electrical paths, giving higher performance • Smaller size gives increased flexibility • Reduced power and cooling requirements • Fewer interconnections increases reliability

32. Growth in CPU Transistor Count

33. IBM 360 series • 1964 • Replaced (& not compatible with) 7000 series • First planned “family” of computers • Similar or identical instruction sets • Similar or identical O/S • Increasing speed • Increasing number of I/O ports (i.e. more terminals) • Increased memory size • Increased cost • Multiplexed switch structure-multiplexor

34. IBM 360 - images

35. DEC PDP-8 • 1964 • First minicomputer (after miniskirt!) • Did not need air conditioned room • Small enough to sit on a lab bench • $16,000 • $100k++ for IBM 360 • Embedded applications & OEM-integrate into a total system with other manufacturers

36. DEC - PDP-8 Bus Structure Universal bus structure (Omnibus)-separate signals paths to carry control, data and address signals Common bus structure- control by CPU

37. Later Generations:Semiconductor Memory • 1950s to 1960s-memory made of ring of ferromagnetic material called cores-fast but expensive, bulky and destructive read • Semiconductor memory-By Fairchild 1970 • Size of a single core • i.e. 1 bit of magnetic core storage • Holds 256 bits • Non-destructive read • Much faster than core • Capacity approximately doubles each year

38. Generations of Computer • Vacuum tube - 1946-1957 Vacuum tube • Transistor - 1958-1964 Transistor • Small scale integration SSI - 1965 on • Up to 100 devices on a chip • Medium scale integration MSI - to 1971 • 100-3,000 devices on a chip • Large scale integration LSI - 1971-1977 • 3,000 - 100,000 devices on a chip • Very large scale integration VLSI - 1978 -1991 • 100,000 - 100,000,000 devices on a chip • Ultra large scale integration ULSI – 1991 - • Over 100,000,000 devices on a chip

39. Microprocessors Intel • 1971 - 4004 • First microprocessor • All CPU components on a single chip • 4 bit design • Followed in 1972 by 8008 • 8 bit • Both designed for specific applications • 1974 - 8080 • Intel’s first general purpose microprocessor • Design to be CPU of a general purpose microcomputer

40. Pentium Evolution - 1 • 8080 • first general purpose microprocessor • 8 bit data path • Used in first personal computer – Altair • 8086 • much more powerful • 16 bit • instruction cache, prefetch few instructions • 8088 (8 bit external bus) used in first IBM PC • 80286 • 16 MB memory addressable • 80386 • First 32 bit design • Support for multitasking- run multiple programs at the same time

41. Pentium Evolution - 2 • 80486 • sophisticated powerful cache and instruction pipelining • built in maths co-processor • Pentium • Superscalar technique-multiple instructions executed in parallel • Pentium Pro • Increased superscalar organization • Aggressive register renaming • branch prediction • data flow analysis • speculative execution

42. Pentium Evolution - 3 • Pentium II • MMX technology • graphics, video & audio processing • Pentium III • Additional floating point instructions for 3D graphics • Pentium 4 • Note Arabic rather than Roman numerals • Further floating point and multimedia enhancements • Itanium • 64 bit • see chapter 15 • Itanium 2 • Hardware enhancements to increase speed • See Intel web pages for detailed information on processors

43. Module 1 Computer System: Designing and Understanding Performance

44. Designing for PerformanceMicroprocessor Speed • Achieve full potential of speed if microprocessor is fed constant data and instructions. Techniques used: • Branch prediction-processor looks ahead in the instruction code and predicts which branches (group of instructions) are likely to be processed next • Data flow analysis-processor analyzes instructions which are dependent on each other’s result or data to create an optimized schedule of instructions • Speculative execution-use branch prediction and data flow analysis, processor speculatively executes instructions ahead of their program execution, holding the result in temporary locations.

45. Performance Balance – Processor and Memory • Performance balance- an adjusting of organization and architecture to balance the mismatch capabilities of various components (etc processor vs. memory) • Processor speed increased • Memory capacity increased • Memory speed lags behind processor speed

46. Performance Balance – Processor and Memory (Performance Gap)

47. Performance Balance – Processor and Memory - Solutions • Increase number of bits retrieved at one time • Make DRAM “wider” rather than “deeper” • Change DRAM interface • Include cache in DRAM chip • Reduce frequency of memory access • More complex and efficient cache between processor and memory • Cache on chip/processor • Increase interconnection bandwidth between processor and memory • High speed buses • Hierarchy of buses

48. Performance Balance: I/O Devices • Peripherals with intensive I/O demands-refer chart • Large data throughput demands-refer chart • Processors can handle this I/O process, but the problem is moving data between processor and devices • Solutions: • Caching • Buffering • Higher-speed interconnection buses • More elaborate bus structures • Multiple-processor configurations

49. Performance Balance: I/O Devices

50. Key is Balance : Designers • 2 factors: • The rate at which performance is changing in the various technology areas (processor, busses, memory, peripherals) differs greatly from one type of element to another • New applications and new peripheral devices constantly change the nature of demand on the system in term of typical instruction profile and the data access patterns