Design of 4-Bit ALU (Philips)

1. Design of 4-Bit ALU (Philips) Group Members Amita Kaur Sethi Craig Chang Deepty Sukumaran Xu Zhou Advisor: Dr. David Parent 12/05/2005

2. Agenda • Abstract • Introduction • Why • Simple Theory • Back Ground information • Summary of Results • Project (Experimental) Details • Results • Cost Analysis • Conclusions

3. Abstract • We designed a functional equivalent of 74HC/HCT181 4-bit ALU whose operational frequency is 200 MHz and used a Power of 19.36 mW • Total area occupied : 406 x 342mm2 • We have used 14 D-Flip Flops at the input side and 8 DFFs on the output side. • The design drives a load up to 25fF

4. Introduction • The ALU performs 16 logic operations and 16 arithmetic operations controlled by four select inputs(S0 to S3) and mode control input M. • Logic operations are performed when M is HIGH and internal carry is inhibited. • When M is LOW, carries are enabled and arithmetic operations are carried out on 4-bit words. • Provides Full Carry Look Ahead for high speed capability for arithmetic operations on long word lengths.

5. Function Table

6. Project Design Flow • Gate Level schematic • NC Verilog Simulation • Longest Path Calculation • Run Spice Simulation for 5% error specification of widths for each component • Layout for each component checking for DRC and LVS errors. • Transistor level Schematic • Designing DFF • Final Layout done with DRC and LVS verification • Post-extracted Simulation

7. Longest Path Calculations

8. Gate-Level Schematic (Overall)

9. Top- Level Schematic

10. DFF Design • 22 D-Flip Flops were used in the entire design • MUX based DFF design was used in this project • Setup time : set up time rise =.712ns set up time fall =.580ns Hold Time : hold time rise = .628ns hold time fall = .696ns Time allocated to each FF= .4ns

11. DFF Sizing

12. DFF Layout

13. Layout (Overall)

14. Final LVS Report net-lists match

15. Test Bench Schematic (Post-Extracted Simulation)

16. Simulation waveform Power =19.36mW

17. Cost Analysis Estimated time taken: 1.verifying logic – 2 days 2.verifying timing - 3 days 3.Cell based designing including DFF design - 4 days 4. Entire Layout with DRC and LVS verification - 6 days 5. Post extracted verification and simulation – 1 day 6. Total time taken from start to finish – 16 days

18. Lessons Learned • Use Cell-based design to avoid layout complications towards the end. • Should have a clear idea about the floor plan before laying out the circuit. • Define cell-size specification before layout. • Use hierarchical design rather than flat for transistor level schematic and layout. • Learned how to debug LVS and DRC errors • Time Management is very important

19. Summary • Our design met all the required specification for power and speed. • Power used =19.36mW • Frequency = 200MHz • The area occupied by design :406 x 342mm2

20. Acknowledgements • Thanks to Cadence Design Systems for the VLSI lab • Thanks to Hummingbird Exceed for remote connectivity. • Thanks to all the group members who worked hard • Professor David Parent for his guidance and support