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4 BIT Arithmetic And Logic Unit (ALU) Philips 74HC/HCT181

4 BIT Arithmetic And Logic Unit (ALU) Philips 74HC/HCT181. Brijesh Chavda Meet Aghera Mrugesh Chandarana Sandip Patel Adviser David Parent Date: 12/03/05. Abstract. Goal is to design 4-bit ALU driving up to 25fF. Perform arithmetic operations like A+B, A+B’, A-1, A+(AB’), AB-1.

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4 BIT Arithmetic And Logic Unit (ALU) Philips 74HC/HCT181

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  1. 4 BIT Arithmetic And Logic Unit (ALU)Philips 74HC/HCT181 Brijesh Chavda Meet Aghera Mrugesh Chandarana Sandip Patel Adviser David Parent Date: 12/03/05

  2. Abstract • Goal is to design 4-bit ALU driving up to 25fF. • Perform arithmetic operations like A+B, A+B’, A-1, A+(AB’), AB-1. • Perform Logical operations like Ex-OR, Compare, AND, NAND, NOR, OR plus 10 other logic operations. • The data must be transferred at clock rate of 200MHz. • Maximum area is 323 X 760 µm².

  3. Introduction • ALU is a building block of several complex circuits. • The designed ALU is able to handle two 4 bit inputs to produce required output based on the output selector lines. • Challenging to design 16 logic level circuit working with 5ns delay. • Using this knowledge and experience, we can move on to designing more complex integrated circuits.

  4. Design Flows • Calculate the longest path delay from the circuit. • Create schematic and layout for INV, NAND2 and NAND3. • Combine these three building blocks to create the different blocks of the circuit. • Test the schematic logic of all the modules. • Assembled all the modules and flip-flops. • Run DRC, extracted and LVS check to verify the design. • Analyze the circuit power and timing using Analog Affirma.

  5. Block diagram of Philips 74HC/HCT181

  6. Longest Path Calculation

  7. Schematic of 4-Bit ALU

  8. Layout of the circuit

  9. Verification – LVS Check

  10. Final TB

  11. Logic Simulation

  12. Lesson learned • Follow the steps and guideline given by Dr. Parent • How to design a compact circuit. • How to fix the LVS errors. • Optimize transistor size to meet out specifications. • How to use cadence tools.

  13. Acknowledgements • Thanks to Professor David Parent for his guidelines and help throughout the project. • Thanks to Cadence Design Systems for VLSI Lab.

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