CMOS Sensor Development

1. CMOS Sensor Development • Guess: CMOS sensors will become detector of choice • Based on commercially useful processes – cheap (relatively) • Inherently radiation hard with enclosed transistors • Low voltage operation (tens vs 100s of volts) • Small dead edge regions • Possibility of stitching to create larger area sensors if needed • Larger area mechanical devices by unstitched multi-reticule cuts • Thinning possible – down to ~50mm • Integrated read-out electronics • Massive cost savings (wire bonds) • Increased reliability • At boundary or integrated into active cells • Or replace wire bonds with capacitive coupling • Existence proofs • Eg STAR – full MAPs • Several prototype pixel sensors for LHC

2. Some Current Problems • Thresholds must be larger than S/N suggest [coherent effects] • (but putting electronics in cell but not in diode seems better) • Single reticule devices are ‘small’ • HR CMOS not demonstrated with back-bias • HV processes tend to have been designed with in-diode electronics • Not much experience • Costs for development • Designers • Submissions (but Moses offers cheap possibilities for development) • Guesses: • Mass small-pitch Bump Bonding not the way of the future • TSVs may have limited use in case of separate R/O & cap coupling • Boundary R/O easier in early implementations • 3-D sensors are tricky by comparison and will not find large-scale application

3. Programmes to develop CMOS both generically and specifically exist • Time scale for ILC probably just about OK • Time scale for LHC upgrades very very tight • For FLC easy • How can Oxford Contribute / become expert • Difficult to maintain own sensor/ASIC design team. • Given proximity to RAL it would also seem a strange thing to do. • Definition of functionality • Testing [incl radiation damage, efficiency …] • Assembly into detectors • Build up suite of test related equipment and folks to use • Probe and bonding facilities • Source, Laser, focussed x-ray, min-I • Alibaba, usbpix, Atlys, - aquire all relevant R/O systems

4. Synergy Development of techniques to make CMOS sensors common Testing kit for CMOS sensors common Very early stages of development possibly common, however Divergent as soon as specific implementations are needed LHC: High rate continuous read-out, moderate power consumption, moderate thickness, triggered read-out ILC: Ultra-thin, power-pulsed, high read-out rate, untriggered FLC: Probably more LHC like

5. Specific proposals • Needs people – try to provide something different to the 10n others • Define appropriate areas [new clean rooms] • Re-commission focussed x-ray system, redesign for CMOS testing • Find a way to make focussed min-I [source or Adams?] • Build/buy highly focussed laser system • Acquire other kit as earlier including wide range of DAQ • Goal of multiple ways to measure efficiencies, charge collection, • signal shapes within pixels with fast turn-around • Lots of money [£100k/year]: • Establish long term relation with RAL TD by continuously employing a designer • to try ideas continuously and asynchronously from specific experiments [like Bonn] • For 200k/year can continuously try design ideas, pursue testing programme.