1 / 40

Lecture 6. CMOS Device (cont)

Lecture 6. CMOS Device (cont). ECE 407/507. Notice. Reading Assignment : chapter 1, chapter 3 (finish reading) Both hw1 and lab1 are on the website hw1 due in one week (next Thurs.) Lab1 due in two week (the Thurs. after next ). The Transistor as a Switch. The Transistor as a Switch.

bina
Download Presentation

Lecture 6. CMOS Device (cont)

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Lecture 6. CMOS Device (cont) ECE 407/507

  2. Notice • Reading Assignment : chapter 1, chapter 3 (finish reading) • Both hw1 and lab1 are on the website • hw1 due in one week (next Thurs.) • Lab1 due in two week (the Thurs. after next )

  3. The Transistor as a Switch

  4. The Transistor as a Switch

  5. The Transistor as a Switch

  6. CGCD C GCS C GCB_1

  7. The Sub-Micron MOS Transistor • Threshold Variations • Subthreshold Conduction • Parasitic Resistances

  8. V V T T Threshold Variations Low V threshold Long-channel threshold DS VDS L Threshold as a function of Drain-induced barrier lowering the length (for low V ) (for low L ) DS

  9. -2 10 Linear -4 10 -6 Quadratic 10 (A) D I -8 10 Exponential -10 10 VT -12 10 0 0.5 1 1.5 2 2.5 V (V) GS Sub-Threshold Conduction The Slope Factor S is DVGS for ID2/ID1 =10 Typical values for S: 60 .. 100 mV/decade

  10. Sub-Threshold ID vs VGS VDS from 0 to 0.5V

  11. Sub-Threshold ID vs VDS VGS from 0 to 0.3V

  12. Summary of MOSFET Operating Regions • Strong Inversion VGS >VT • Linear (Resistive) VDS <VDSAT • Saturated (Constant Current) VDS VDSAT • Weak Inversion (Sub-Threshold) VGS VT • Exponential in VGS with linear VDS dependence

  13. Parasitic Resistances

  14. Future Perspectives 25 nm FINFET MOS transistor

  15. New Tech: Silicon On Insulator (SOI) • Silicon wafers are highly perfect : critically important for achieving high device yield. • But a more radical change may be needed in the material structure, processing method, or device design in order to enhance the circuit performance.

  16. Why use SOI • Extend the life of traditional silicon technology • Boost speed • Reduce power consumption • Solve some scaling difficulties

  17. Transistor crosssection

  18. SOI material structure

  19. Benefits of SOI -performance

  20. Benefits of SOI -- power

  21. Benefits of SOI – timing

  22. SiGe: Silicon Germanium • Used to be inefficient in chip production • Extremely high frequencies: 60Ghz • Very little power usage • 70% faster, 35% less power

  23. Why SiGe The layer of latticed silicon and germanium added to the chips silicon layer increases the distance between silicon atoms Less force between atoms, easy for electrons to pass by with less resistance IBM suggests combining SiGe and SOI

  24. Thermal problem with SiGe The diagram above shows the effect of localized self-heating in the emitters (30C for 40mv)

More Related