Reconfigurable Computing (EN2911X, Fall07) Lecture 06: Verilog (2/3)

1. Reconfigurable Computing (EN2911X, Fall07) Lecture 06: Verilog (2/3) Prof. Sherief Reda Division of Engineering, Brown University http://ic.engin.brown.edu

2. Dataflow modeling • Module is designed by specifying the data flow, where the designer is aware of how data flows between hardware registers and how the data is processed in the design • The continuous assignment is one of the main constructs used in dataflow modeling • assign out = i1 & i2; • assign addr[15:0] = addr1[15:0] ^ addr2[15:0]; • assign {c_out, sum[3:0]}=a[3:0]+b[3:0]+c_in; • A continuous assignment is always active and the assignment expression is evaluated as soon as one of the right-hand-side variables change • Left-hand side must be a scalar or vector net. Right-hand side operands can be registers, nets, integers, real, …

3. Operator types in dataflow expressions • Operators are similar to C except that there are no ++ or – • Arithmetic: *, /, +, -, % and ** • Logical: !, && and || • Relational: >, <, >= and <= • Equality: ==, !=, === and !== • Bitwise: ~, &, |, ^ and ^~ • Reduction: &, ~&, |, ~|, ^ and ^~ • Shift: <<, >>, >>> and <<< • Concatenation: { } • Replication: {{}} • Conditional: ?:

4. Example module mux4(out, i0, i1, i2, i3, s1, s0); output out; input i0, i1, i2, i3; output s1, s0; assign out = (~s1 & ~s0 & i0) | (~s1 & s0 & i1) | (s1 & ~s0 & i2) | (s1 & s0 & i3); // OR THIS WAY assign out = s1 ? (s0 ? i3:i2) : (s0 ? i1:i0); endmodule

5. Design is expressed in algorithmic level, which frees designers from thinking in terms of logic gates or data flow. Designing at this model is very similar to programming in C. All algorithmic statements in Verilog can appear only inside two statements: always and initial. Each always and initial statement represents a separate activity flow in Verilog. Remember that activity flows in Verilog run in parallel. You can have multiple initial and always statements but you can’t nest them. Behavioral or algorithmic modeling . . reg a, b, c; initial a=1’b0; . . always begin b = a ^ 1’b1; c = a + b; end . .

6. An initial block start at time 0, executes exactly once and then never again. If there are multiple initial blocks, each blocks starts to execute concurrently at time 0 and each blocks finish execution independently of the others. Multiple behavioral statements must be grouped using begin and end. If there is one statement then grouping is not necessary. initial statements reg x, y, m; initial m=1’b0; initial begin x=1’b0; y=1’b1; end

7. The always statement starts at time 0 and executes the statements in the always block continuously in a looping fashion. It models a block of activity that is repeated continuously in a digital circuit. Multiple behavioral statements must be grouped using begin and end. If there is one statement then grouping is not necessary. always statement integer count; count=0; always begin count=count+1; end

8. Events-based timing control • An event is the change in the value on a register or a net. Events can be utilized to trigger the execution of a statement of a block of statements. • The @ symbol is used to specify an event control. • Statements can be executed on changes in signal value or at a positive (posedge) or negative (negedge) transition of the signal. input clock; integer count; count=0; always @(clock) begin count=count+1; end input clock; integer count; count=0; always @(clock) begin count=count+1; end input clock1, clock 2; integer count; count=0; always @(clock1 or clock2) begin count=count+1; end

9. Procedural assignments update values of reg, integer, or real variables. The value will remain unchanged until another procedural assignment updates the variable with a different value → different from dataflow continuous assignments. Two types of procedural assignments: blocking and nonblocking. Procedural assignments Blocking statements, specified using the = operator, are executed in the order they are specified in a sequential block. Nonblocking statements, specified using the <= operator, are executed without blocking the statements that flow in a sequential block. reg x, y; initial begin x<=1’b1; y<=1’b0; end reg x, y; initial begin x=1’b1; y=1’b0; end

10. Uses of nonblocking assignments If the intention is to swap the contents of and b, which one of these will work? always @(posedge clock) begin a = b; b = a; end always @(posedge clock) begin a <= b; b <= a; end Nonblocking assignments eliminate the race conditions. At the positive edge of clock, the values of all the RHS variables are “read”, expressions evaluated and then assigned to the LHS.

11. Very similar to C Can always appear inside always and initial blocks Conditional statements . if(alu_control == 0) y = x + z; else if (alu_control == 1) y = x – z; else if (alu_control == 2) y = x * z; else y = x; . . if(x) begin y= 1’b1; z= 1’b0; end . if (count < 10) count = count+1; else count = 0; . expression reg [1:0] alu_control; .. case (alu_control) 2’d0 : y = x + z; 2’d1 : y = x – z; 2’d2 : y = x * z; default: y=x; endcase

12. Loops integer count; integer y=1; integer x=2; initial for (count = 0; count < 128; count = count + 1) begin x <= x + y; y <= x; end initial count = 0; repeat(128) begin . . count = count +1; end initial count = 0; while (count < 128) begin . . count = count +1; end Must contain a number or a signal value; only evaluated once at the beginning

13. Example: Mux4x1 module mux4x1(out, i0, i1, i2, i3, s1, s0); output out; input i0, i1, i2, i3; input s1, s0; reg out; always @(s1 or s0 or i0 or i1 or i2 or i3) begin case({s1, s0}) 2’d0: out = i0; 2’d1: out = i1; 2’d2: out = i2; 2’d3: out = i3; endcase endmodule

14. DE2 board overview CLOCK_50 HEX0[6:0] … HEX7[6:0] LEDG[0] … LEDG[8] LEDR[0] … LEDR[17] SW[0] … SW[17] KEY[0] … KEY[3] Import the given pin assignment file to make things easy for you!

15. D2 example: A 1 second blinking light module sec (input CLOCK_50, output reg [8:0] LEDG); integer count=0; initial LEDG[0]=1'b0; always @(posedge CLOCK_50) begin count=count+1; if(count == 50_000_000) begin count=0; if(LEDG[0]) LEDG[0]=1'b0; else LEDG[0]=1'b1; end end endmodule

16. Please go through the lab0 tutorial to get familiar with the tool and the synthesis environment Please check the class webpage for helpful resources You are required to form teams (2 students per team). Since there are 11 students enrolled in the class, one team has to be composed of either 3 students or just 1 student. Deliverables (1st game Oct 4th and 2nd game Oct 9th) include Working design which will be tested Quartus II project files Written documentation includes Verilog source code with comments Report the amount of logic and routing area utilized in the FPGA Snapshot of the final layout of the FPGA as produced by the synthesis tool Simple documentations on any additions you volunteered to add to the game Lab 1

17. The objective of this game to memorize a “random” pattern of lights that is displayed to you on the DE2 board LEDs, and input it back using the available push buttons or switches. At the beginning, the board should display the user a pattern by lighting one LED at a time for a “short” period, and then the gamer should input back the pattern in the same sequence. After that, the board should display some sign on the 7 segment display to tell the gamer whether his/her input is correct or not, and replay with another “random pattern.” There are two knobs that you can use to make the game harder: the period where each LED is ON and the length of the pattern. You can either fix those in advance, or make change them as the user progresses in playing. Game 1: Secret Code Grabber AKA Simon

18. In this game we have an ant that continuously traverses the board from left to right and then from right to left. The position of the ant is indicated by the LED that is lightened up. The ant is quick and stops at each position for a “short” period. The ant also sometimes “randomly” changes its direction which makes it hard to predict its next location. Your objective is to catch the ant as many times as you could. Each position corresponds to a push button and you want to press the push button that corresponds to the ant position. Every time you correctly get the ant, you score 1 point and every time you miss you lose 1 point. The score should be displayed on the seven segments. Game 2: Catch the ant

19. In this game the DE2 board is possessed by some alien. It displays some alien symbol on one of the 7 segment displays and then displays four symbols on four other 7 segment displays. Your objective is to choose (via the push buttons) the number (or location) of the symbol that matches the alien symbol. You have to be quick because the board will allow you only very “short” time to make your choice. A green LED should lighten up if you match successfully; otherwise, a red LED should lighten up. Game 3: Match the alien symbol