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BJT Fixed Bias. ENGI 242 ELEC 222. BJT Biasing 1. For Fixed Bias Configuration: Draw Equivalent Input circuit Draw Equivalent Output circuit Write necessary KVL and KCL Equations Determine the Quiescent Operating Point Graphical Solution using Loadlines Computational Analysis
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BJT Fixed Bias ENGI 242 ELEC 222
BJT Biasing 1 For Fixed Bias Configuration: • Draw Equivalent Input circuit • DrawEquivalent Output circuit • Write necessary KVL and KCL Equations • Determine the Quiescent Operating Point • Graphical Solution using Loadlines • Computational Analysis • Design and test design using a computer simulation ENGI 242/ELEC 222
Complete CE Amplifier with Fixed Bias ENGI 242/ELEC 222
Fixed Bias and Equivalent DC Circuit ENGI 242/ELEC 222
Fixed-Bias Circuit ENGI 242/ELEC 222
DC Equivalent Circuit ENGI 242/ELEC 222
Base-Emitter (Input) Loop Using Kirchoff’s voltage law: – VCC + IBRB + VBE = 0 Solving for IB: ENGI 242/ELEC 222
Collector-Emitter (Output) Loop Since: IC = IB Using Kirchoff’s voltage law: – VCC + IC RC + VCE = 0 Because: VCE = VC – VE Since VE = 0V, then: VC = VCE AndVCE =VCC - IC RC Also: VBE = VB - VE with VE = 0V, then: VB = VBE ENGI 242/ELEC 222
BJT Saturation Regions When the transistor is operating in the Saturation Region, the transistor is conducting at maximum collector current (based on the resistances in the output circuit, not the spec sheet value) such that: ENGI 242/ELEC 222
Determining Icsat ENGI 242/ELEC 222
Determining ICSAT for the fixed-bias configuration ENGI 242/ELEC 222
Load Line Analysis ENGI 242/ELEC 222
Load Line Analysis • The end points of the line are : ICsat and VCEcutoff • For load line analysis, use VCE = 0 for ICSAT, and IC = 0 for VCEcutoff • ICsat: • VCEcutoff: • Where IB intersects with the load line we have the Q point • Q-point is the particular operating point: • Value of RB • Sets the value of IB • Where IB and Load Line intersect • Sets the values of VCE and IC. ENGI 242/ELEC 222
Circuit values effect Q-point ENGI 242/ELEC 222
Circuit values effect Q-point (continued) ENGI 242/ELEC 222
Circuit values effect Q-point (continued) ENGI 242/ELEC 222
Load-line analysis ENGI 242/ELEC 222
DC Fixed Bias Circuit Example ENGI 242/ELEC 222
Loadline Example Family of Curves ENGI 242/ELEC 222
Emitter Stabilized Bias ENGI 242 ELEC 222
BJT Emitter Bias For the Emitter Stabilized Bias Configuration: • Draw Equivalent Input circuit • DrawEquivalent Output circuit • Write necessary KVL and KCL Equations • Determine the Quiescent Operating Point • Graphical Solution using Loadlines • Computational Analysis • Design and test design using a computer simulation ENGI 242/ELEC 222
Improved Bias Stability • The addition of RE to the Emitter circuit improves the stability of a transistor output • Stability refers to a bias circuit in which the currents and voltages will remain fairly constant over a wide range of temperatures and transistor forward current gain () • The temperature (TA or ambient temperature) surrounding the transistor circuit is not always constant • Therefore, the transistor is not a constant value ENGI 242/ELEC 222
Emitter-Stabilized Bias Circuit Adding an emitter resistor to the circuit between the emitter lead and ground stabilizes the bias circuit over Fixed Bias ENGI 242/ELEC 222
Base-Emitter Loop ENGI 242/ELEC 222
Equivalent Network ENGI 242/ELEC 222
Reflected Input impedance of RE ENGI 242/ELEC 222
Base-Emitter Loop Applying Kirchoffs voltage law: - VCC + IB RB + VBE +IE RE = 0 Since: IE = ( + 1) IB We can write: - VCC + IB RB + VBE + ( + 1) IBRE = 0 Grouping terms and solving for IB: Or we could solve for IE with: ENGI 242/ELEC 222
Collector-Emitter Loop ENGI 242/ELEC 222
Collector-Emitter Loop Applying Kirchoff’s voltage law: - VCC + IC RC + VCE + IE RE = 0 Assuming that IE IC and solving for VCE: VCE=VCC – IC (RC + RE) If we can not use IE IC the IC = IE and:VCE=VCC – IC (RC + RE) Solve for VE: VE = IE RE Solve for VC: VC = VCC - IC RC or VC = VCE + IE RE Solve for VB: VB = VCC - IB RB or VB = VBE + IE RE ENGI 242/ELEC 222
Transistor Saturation At saturation, VCE is at a minimum We will find the value VCEsat = 0.2V For load line analysis, we use VCE = 0 To solve for ICSAT, use the output KVL equation: ENGI 242/ELEC 222
Load Line Analysis The load line end points can be calculated: At cutoff: At saturation: ENGI 242/ELEC 222
Emitter Stabilized Bias Circuit Example ENGI 242/ELEC 222
Design of an Emitter Bias CE Amplifier Where .1VCC VE .2VCC And .4VCC VC .6VCC ENGI 242/ELEC 222
Emitter Bias with Dual Supply ENGI 242/ELEC 222
Emitter Bias with Dual Supply Input Output ENGI 242/ELEC 222