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VERSATILE VIDEO DECODING

Brussels Meeting - 23 November, 2005. 2. Outline. IntroductionState of the artWhy current decoder architectures are inadequateArchitectural requirements, solution and innovationSystem on chip challenges for integrated IPDecoder IP (macrocell) architectureMulti-standard operator example : IPF

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VERSATILE VIDEO DECODING

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    1. VERSATILE VIDEO DECODING Joint Consortium Meeting 23 November, 2005, Brussels

    2. Brussels Meeting - 23 November, 2005 2 Outline Introduction State of the art Why current decoder architectures are inadequate Architectural requirements, solution and innovation System on chip challenges for integrated IP Decoder IP (macrocell) architecture Multi-standard operator example : IPF Verification challenge Conclusion

    3. Brussels Meeting - 23 November, 2005 3 Introduction – state of the art MPEG2 : Stable technology MPEG2 deployed for more than 10 years HW architecture was a good compromise Efficient and powerful for a single standard dominating digital video world A new emerging standard for consumer market : H264 H264 early emerged as a potential replacement of MPEG2 for consumer market Requirement for early presence required quick solutions Non optimized Heavily hardwired as per experience of SoC companies Initial System on Chip solutions embedding both fast H264 solutions with MPEG2 legacy decoders

    4. Brussels Meeting - 23 November, 2005 4 Introduction – reasons to move Several factors lead to look for a versatile solution Competition of several standards for new generation of codecs (H264, VC1) More optimized solution to ensure backward compatibility with previous standard (MPEG2) Additional codecs to become more and more necessary for any kind of digital consumer product (DivX, DV) Need of multi-standard implementation In the mean time, processor capacity making versatile solution possible Increase of low cost embedded processor speed HD resolution at 400MHz means 4.3 cycle per pixel or 1600 cycle per MB SD resolution at 400MHz means 26 cycle per pixel or 9800 cycle per MB Usage of processor for MB operations (HD) or pixel operations (SD) feasible

    5. Brussels Meeting - 23 November, 2005 5 Video decoder system Overall stream decoder implemented in two parts Control and data processing Software video driver All decoding above and down to picture level Managing picture decoder through a picture instruction Managing all frame handling beside decoding, all presentation parameters (synchronization, display aspects and resize) Managing local memory map and buffers Controlling transport and PES layer engine Video decoder handling all picture decoding from the picture instruction generating frame buffer in local memory

    6. Brussels Meeting - 23 November, 2005 6 Moving towards multi video format A Driver architecture adapted to support any video format High level generic stream video interface to adapt to any application or middleware Generic stream decoder for input buffers and transport layer control, synchronization and display control Specific layer to handle the video decoder engine and handle specific characteristics of standards (high level syntax, picture buffer management)

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