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Chapter 2

Chapter 2. 3. 8, 2012. 2 approaches in studying the design of ICs. Begin with quantum mechanics and understand solid-state physics, semiconductor device physics, device modeling, and finally the design of circuits

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Chapter 2

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  1. Chapter 2 3. 8, 2012

  2. 2 approaches in studying the design of ICs. • Begin with quantum mechanics and understand solid-state physics, semiconductor device physics, device modeling, and finally the design of circuits • Treat each semiconductor device as a black box whose behavior is described in terms of its terminal voltages and currents and design circuits with little attention to the internal operation of the device. • Neither approach is optimum. • In today’s IC industry, a solid understanding of semiconductor devices is essential. • Develop a circuit model for each device by formulating its operation.

  3. 2.1 General Consideration 2.1.1 MOSFET as a Switch • What is the “threshold” voltage? …. Figure 2.1 Simple view of a MOS device Gate Source Drain

  4. 2.1.2 MOSFET Structure • NMOS: p-type substrate (also called “bulk” or “body”), heavily-doped n regions, heavily-doped piece of polysilicon, a thin layer of SiO2 • The useful action of the device occurs in the substrate region under the gate oxide.

  5. Due to the S/D junction “side-diffuse”, Leff = Ldrawn – 2LD • Leffand tox play an important role in the performance of MOS circuits. • In reality, the substrate potential greatly influences the device characteristics.  4 terminal device • The actual connection is usually provided through an ohmic p+ region.

  6. In practice, NMOS and PMOS devices must be fabricated on the same wafer (same substrate).  One device type can be placed in a “local substrate”, usually called a “well”. • The n-well is tied to the most positive supply voltage.

  7. 2.1.3 MOS Symbols

  8. 2.2 MOS I/V Characteristics 2.2.1 Threshold Voltage • What happens as VG increases from 0?

  9. A depletion region  No current flows. • When the interface potential reaches a sufficiently positive value, electrons flow from the source to the interface an eventually to the drain. • The interface is “inverted”.  threshold VG = VTH • VTH of NFET is usually defined as the VG for which the interface is “as much n-type as the substrate is p-type.” ФMS: the difference between the work function of the polysilicon gate and the silicon substrate.

  10. Nsub:the doping concentration of the substrate Qdep: the charge in the depletion region Cox: the gate oxide capacitance per unit area. From pn junction theory, tox≈ 50Å, Cox ≈ 6.9fF/μm2

  11. In practice, VTH is typically adjusted by implantation of dopants into the channel area during device fabrication, in essence altering the doping level of the substrate near the oxide interface. • If a thin sheet of p+ is created, VG required to deplete this region increases.

  12. In Fig.2.6(a), only ID can indicate whether the device is “on” or “off,” thus failing to reveal as what VGS the interface is as much n-type as the bulk is p-type. • The calculation of VTH from I/V measurement is somewhat ambiguous. • For PFET

  13. 2.2.2 Derivation of I/V Characteristics • If the charge density along the direction of current is QdC/m, the velocity of the charge is v m/sec, I = Qd v

  14. Consider Fig. 2.10(a) Qd = WCox(VGS – VTH) • Suppose Fig. 2.10(b)

  15. The local voltage difference between the gate and the channel varies from VG to VG – VD.

  16. Peak occurs at VDS = VGS – VTH VGS – VTH: overdrive voltage, W/L: aspect ratio

  17. If VDS <<2(VGS – VTH) • This linear relationship can be represented by a linear resistor

  18. Ex 2.1 • VTH = 0.7 V, the drain terminal is open. Ron = ?

  19. What happens if VDS>VGS – VTH ? • Saturation region

  20. If VDS is slightly greater than VGS – VTH, then the inversion layer stops at x≤L.  “pinched off” • Where L' is the point at which Qddrops to 0, • ID is relatively independent of VDS if L' remains close to L. • For PMOS devices,

  21. With L ≈ L', a saturated MOSFET can be used as a current source.

  22. A figure of merit, “transconductance” • gm in the saturation region = 1/Ron in deep triode region. • Also,

  23. Ex 2.2

  24. 2.3 Second-Order Effects Body Effect • What happens if the bulk voltage of an NFET drops below the source voltage? • Suppose VS = VD = 0, VG is somewhat less than VTH so that a depletion region is formed but no inversion layer exists.

  25. As VB drops and Qd increases, VTH also increases.  body effect or backgate effect where VTHO from (2.1).

  26. Ex. 2.3 plot the drain current if ∞<VX <0.

  27. For body effect to manifest itself, the bulk potential, Vsub, need not change. • In Fig. 2.24(a), as Vin varies, Vout closely follows the input because ID remains equal to I1.  Vin – Vout is constant if I1 is constant.

  28. Now suppose the substrate is tied to ground and body effect is significant.  Vin – Vout must increase. • Body effect is usually undesirable. Channel-Length Modulation • L' is in fact a function of VDS. • Assuming a 1st-order relationship between ΔL/L and VDSsuch as ΔL/L = λVDS, in saturation,

  29. Nonzero slope in the ID/VDS hence a nonideal current source.

  30. Ex 2.4 • Keeping all other parameters constant, plot ID/VDS for L = L1 and L = 2L1.

  31. Subthreshold Conduction • For VGS≈ VTH, a “week” inversion layer still exists and some current flows from D to S. • Even for VGS<VTH, IDis finite, but it exhibits an exponential dependence on VGS.  subthreshold conduction • For VDS greater than roughly 200 mV • We also say the device in “week inversion”

  32. When VGS is reduced to 0, ID decreases by only a factor of 103.75. • In large circuits (memories), this can result in significant power dissipation.

  33. Voltage Limitations • Various breakdown effects if their terminal voltage differences exceed certain limits. • At high VGS, the gate oxide breaks down irreversibly. • In short-channel devices, an excessively large VDS widens the depletion region around the drain so much that it touches that around the source, creating a very large drain current.  punchthrough

  34. 2.4 MOS Device Models 2.4.1 MOS Device Layout • The source and drain junctions play an important role in the performance. • To minimize the capacitance of S and D, the total area of each junction must be minimized.

  35. Ex 2.5 Draw the layout of the circuit Fig. 2.29(a)

  36. 2.4.2. MOS Device Capacitances • The capacitances associated with the devices must also be take into account so as to predict the “ac” behavior as well.

  37. C1 = WLCox

  38. Ex 2.6 Calculate the S & D junction capacitances

  39. Ex 2.7 Sketch the capacitances of M1

  40. 2.4.3 MOS Small-Signal Model • Large signal significantly disturbs the bias points. • By contrast, if the perturbation in bias condition is small, a small-signal model (approximation of the large-signal model around the operating point), can be employed to simplify the calculations. • In many analog circuits, MOSFETs are biased in saturation region. • Owing to channel-length modulation, ID also varies with VDS. This can be done by

  41. The model in Fig. 2.36(d) is adequate for most low-frequency small-signal analyses. In reality, each terminal of a MOSFET exhibits a finite ohmic resistance resulting from the resistivity of the material (and the contacts), but proper layout can minimize such resistances.

  42. Complete MOS small-signal model

  43. Ex 2.8 Sketch gm and gmb of M1 vs I1

  44. 2.4.4 MOS SPICE models

  45. 2.4.5 NMOS vs PMOS Devices • PMOS devices are quite inferior to NMOS transistors. • μpCox ≈ 0.25μnCox • NMOS exhibits a higher output resistance.

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