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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Dual-Threshold Low-Power Devices. Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

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  1. ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsDual-Threshold Low-Power Devices Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC5970-001/6970-001 Lecture 5

  2. Subthreshold Conduction Vgs – Vt -Vds Ids = I0 exp( ───── ) × (1– exp ── ) nvth vth Ids 1mA 100μA 10μA 1μA 100nA 10nA 1nA 100pA 10pA Sunthreshold slope Saturation region Subthreshold region Vt 0 0.3 0.6 0.9 1.2 1.5 1.8 V Vgs ELEC5970-001/6970-001 Lecture 5

  3. Thermal Voltage, vth vth = kT/q = 26 mV, at room temperature. When Vds is several times greater than vth Vgs – Vt Ids = I0 exp( ───── ) nvth ELEC5970-001/6970-001 Lecture 5

  4. Leakage Current • Leakage current equals Ids when Vgs= 0 • Leakage current, Ids = I0exp(-Vt /nvth) • At cutoff, Vgs = Vt, and Ids = I0 • Lowering leakage to 10-kI0 Vt = knvth ln 10 = 1.5× 26 ln 10 = 90k mV • Example: To lower leakage to I0/1,000 Vt = 270 mV ELEC5970-001/6970-001 Lecture 5

  5. Threshold Voltage • Vt = Vt0 + γ[(Φs+Vsb)½- Φs½] • Vt0 is threshold voltage when source is at body potential (0.4 V for 180nm process) • Φs = 2vth ln(NA/ni) is surface potential • γ = (2qεsiNA)½tox/εox is body effect coefficient (0.4 to 1.0) • NA is doping level = 8×1017 cm-3 • ni = 1.45×1010 cm-3 ELEC5970-001/6970-001 Lecture 5

  6. Threshold Voltage, Vsb=1.1V • Thermal voltage, vth = kT/q = 26 mV • Φs = 0.93 V • εox = 3.9×8.85×10-14 F/cm • εsi = 11.7×8.85×10-14 F/cm • tox = 40 Ao • γ = 0.6 V½ • Vt = Vt0 + γ[(Φs+Vsb)½- Φs½] = 0.68 V ELEC5970-001/6970-001 Lecture 5

  7. A Sample Calculation • VDD = 1.2V, 100nm CMOS process • Transistor width, W = 0.5μm • OFF device (Vgs = Vt) leakage • I0 = 20nA/μm, for low threshold transistor • I0 = 3nA/μm, for high threshold transistor • 100M transistor chip • Power = (100×106/2)(0.5×20×10-9A)(1.2V) = 600 mW, for all low-threshold transistors • Power = (100×106/2)(0.5×3×10-9A)(1.2V) = 90 mW, for all high-threshold transistors ELEC5970-001/6970-001 Lecture 5

  8. Dual-Threshold Chip • Low-threshold only for 20% transistors on critical path. • Leakage power = 600×0.2 + 90×0.8 = 120 + 72 = 192 mW ELEC5970-001/6970-001 Lecture 5

  9. Dual-Threshold CMOS Circuit ELEC5970-001/6970-001 Lecture 5

  10. Dual-Threshold Design • To maintain performance, all gates on the critical path are assigned low Vt. • Most of the other gates are assigned high Vt. But, • Some gates on non-critical paths may also be assigned low Vt to prevent those paths from becoming critical. ELEC5970-001/6970-001 Lecture 5

  11. Integer Linear Programming (ILP) to Minimize Leakage Power • Use dual-threshold CMOS process • First, assign all gates low Vt • Use an ILP model to find the delay (Tc) of the critical path • Use another ILP model to find the optimal Vt assignment as well as the reduced leakage power for all gates without increasing Tc • Further reduction of leakage power possible by letting Tc increase ELEC5970-001/6970-001 Lecture 5

  12. ILP -Variables For each gate i define two variables. • Ti:the longest time at which the output of gate i can produce an event after the occurrence of an input event at a primary input of the circuit. • Xi:a variable specifyinglow or high Vt for gate i; Xi is an integer [0, 1]. 1  gate i is assigned low Vt; 0  gate i is assigned high Vt. ELEC5970-001/6970-001 Lecture 5

  13. ILP - objective function Leakage power: - minimize the sum of all gates leakage currents, given by • ILi is the leakage current of gate i with low Vt; • IHiis the leakage current of gate i with high Vt; • Using SPICE simulation results, construct a leakage current look up table, which is indexed by the gate type and the input vector. ELEC5970-001/6970-001 Lecture 5

  14. ILP - Constraints • For each gate (1) gate j ‘s output is gate i ‘s fan in (2) • Max delay constraints for primary outputs (PO) (3) Tmax is the maximum delay of the critical path ELEC5970-001/6970-001 Lecture 5

  15. ILP Constraint Example • assume all primary input (PI) signals on the left arrive at the same time. • For gate 2, constraints can be given by ELEC5970-001/6970-001 Lecture 5

  16. ILP – Constraints (cont.) • DHi is the delay of gate i with high Vt • DLi is the delay of gate i with low Vt • A second look-up table is constructed and specifies the delay for given gate type and fanout number. ELEC5970-001/6970-001 Lecture 5

  17. ILP – Finding Critical Delay • Tmaxcan be specified or be the delay of longest path (Tc). • To find Tc, we change constraints (2) to an equation, assigning all gates with low Vt. • Maximum Ti in the ILP solution is Tc. • If we replace Tmaxwith Tc, the objection function minimizes leakage power without sacrificing performance. ELEC5970-001/6970-001 Lecture 5

  18. If we gradually increase Tmax from Tc, leakage power is further reduced, because more gates can be assigned high Vt. But, the reduction trends to become slower. When Tmax = (130%) Tc, the reduction is about saturated, because almost all gates are assigned high Vt. Maximum leakage reduction can be 98%. Power-Delay Tradeoff ELEC5970-001/6970-001 Lecture 5

  19. Power-Delay Tradeoff ELEC5970-001/6970-001 Lecture 5

  20. Leakage Reduction ELEC5970-001/6970-001 Lecture 5

  21. Dynamic & Leakage Comparison • vth (thermal voltage, kT/q) and Vt both depend on the temperature; leakage current also strongly depends on temperature. • Spice simulation shows that for a 2-input NAND gate - with low Vt, Isub @ 90ºC = 10 × Isub @ 27ºC - with high Vt, Isub @ 90ºC = 20 × Isub @ 27ºC • To manifest the projected contribution of leakage to the total power, we compare dynamic and leakage power @ 90ºC. ELEC5970-001/6970-001 Lecture 5

  22. Results-Dynamic & Leakage Comparison (cont.) • Without considering glitches, the dynamic power is estimated by an event driven simulator, and is given by • We apply 1000 random test vectors at PIs with a vector period of 120% Tc, and calculate the total number of weighted (by node capacitance) transitions in the circuit. ELEC5970-001/6970-001 Lecture 5

  23. Dynamic & Leakage Power (cont.) ELEC5970-001/6970-001 Lecture 5

  24. Dynamic & Leakage Power (cont.) ELEC5970-001/6970-001 Lecture 5

  25. Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vt Assignment and Path Balancing Yuanlin Lu VLSI Design and Test Seminar Broun 235 September 14, 2005, 3:00PM ELEC5970-001/6970-001 Lecture 5

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