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USB On-The-Go Implementation Trade-offs

USB On-The-Go Implementation Trade-offs. Zong Liang WU TransDimension. Agenda. On-The-Go device vs. Dual role device Dual role device: top level architecture Basic issues: system constraints System constraints vs. Implementation choices Compliance & interoperability Product decision.

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USB On-The-Go Implementation Trade-offs

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  1. USB On-The-Go Implementation Trade-offs Zong Liang WU TransDimension

  2. Agenda • On-The-Go device vs. Dual role device • Dual role device: top level architecture • Basic issues: system constraints • System constraints vs. Implementation choices • Compliance & interoperability • Product decision

  3. On-The-Go Device Vs. Dual Role Device • Dual role device (DRD): • Supports master negotiation protocol • Acts as master or slave, after MNP • Capable of supplying at least 4mA • On-The-Go device (OTG): • Dual Role Device • Slave-only device drawing less than 4mA from Vbus

  4. Dual Role DeviceTop-Level Architecture Charge Pump 5V @4mA Processor Interface System processor HOST Analog Transceiver Cable Function MNP Registers Top level control

  5. Basic IssuesSystem Constraints • Microprocessors • Wide range of performance (uP itself or the part available for DRD) • Different interfaces: often DRD is not allowed to be system bus master • System software • Latency of HW interrupt processing • Maybe critical for Isochronous applications • Different RTOS

  6. System Constraints Vs.Implementation Choices • Performance of the master: • Throughput supported: full 12mbits/s (as good as or even better than a PC) vs. Very limited bandwidth • Endpoint types supported: all 4 types vs. A subset • Number of devices and endpoints supported: capable of supporting many devices/endpoints simultaneously vs. Onlya few endpoints • Difficulties: • How to get maximum master performance with a limited uP? • How to do in embedded applications where DRD is not allowed to be system bus master ? • How to support Isochronous applications within a RTOS having a large interrupt latency (like wince)?

  7. System Constraints Vs.Implementation Choices • uP requirements vs. Master performance: • Desired target for portable or STB applications: • Optimal performance • Light load on uP • Minimum interrupt frequency • Loose requirement on uP’s interrupt latency • Keep at low cost (HW+SW) • Trade-off vs. Smart SW/HW partitioning Learn from OHCI and UHCI partitioning • Call for major architecture innovation

  8. System Constraints Vs.Implementation Choices • Many applications: • Portable (PDA, mobile phone, MP3, pocket PC, digital camera etc)and less portable (set-top-box, game machine, etc): • Many RTOS on the market • RTOS-based stack vs. Dedicated system SW • RTOS is not always necessary • Think of a dedicated microprocessor • RTOS-based: how to design once for all? • Try to comply with and reuse OHCI/UHCI stack • Partner with specialty system software house

  9. System Constraints Vs.Implementation Choices • Power management: • Portable appliances require low power • OTG spec introduces the concept of sessionand wakeup protocol • Manage power at chip architecture level, by introducing appropriate power management logic

  10. System Constraints Vs.Implementation Choices • Single chip vs. 2-chip solution • OTG master needs to supply 5V@4mA (minimum) • Analog transceiver’s signaling is 3.3V • Standard 0.18um process has trouble to implement • Put the charge pump and the analog transceiverinto a separate chip • Define a standard interface: ongoing effort

  11. Compliance & Interoperability • Compliance to WHAT: • A DRD must be a 100% compliant USB function • OTG master vs. Embedded master vs. StandardPC host (OHCI/UHCI): • OTG: one to one: simpler master • Embedded: Strong sales point if the master cansupport what a standard PC host can do(endpoint types, number, sizes) • An OTG compliance spec is in development

  12. Product Decision • What do you really want: • Slave-only with mini-connector and draws <=4ma • Dual role device (master or slave depending on MNP result) • Simultaneous master and slave • Do not forget your expectation on master’s performance • Discrete IC or integrate an IP into your system: • Time to market vs. Cost vs. Risk

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