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COURS DE DSP (Digital Signal Processor) Partie 2: architecture Alain Fruleux

COURS DE DSP (Digital Signal Processor) Partie 2: architecture Alain Fruleux. I S E N 2006. 1- DEVELOPPEMENT A PARTIR DE DSP. 1.1 Du µP au DSP Quelle famille!!! µP Microprocesseurs µC Microcontrôleurs DSP Digital Signal Processeur Risc/Cisc…..8/16/32/64 bits.

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COURS DE DSP (Digital Signal Processor) Partie 2: architecture Alain Fruleux

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  1. COURS DE DSP(Digital Signal Processor)Partie 2: architectureAlain Fruleux I S E N 2006

  2. 1- DEVELOPPEMENT A PARTIR DE DSP. • 1.1 Du µP au DSP Quelle famille!!! • µP Microprocesseurs • µC Microcontrôleurs • DSP Digital Signal Processeur • Risc/Cisc…..8/16/32/64 bits

  3. 1.1.1 µprocesseur story

  4. Add Multiply 1+2 = 3 5*3 = 15 0001 0101 0011001100110011 xxxx 8421 xxxx 0000 0011 0000 0011 0010 + 0011 Shifted and added multiple times 3 5 = MAC Operation Most Common Operation in DSP A = B*C + D Typically 70 Clock Cycles With Ordinary Processors E = F*G + A . . . Multiply, Add, and Accumulate Typically 1 Clock Cycle With Digital Signal Processors MAC Instruction 1.1.2 Spécificités du DSP (MAC)

  5. 2 - Structure d ’un Système à DSP (µP) • 2-1 Vision Globale du DSK/TMS320C5510 de TI • 2-2 Architecture d ’une carte DSP • 2-3 Voyage au centre du DSP • et parallélisme

  6. 2-0 Vision Globale DSK/TMS320c5510 de TI • ? • ? • ? • ? • ?

  7. 2-1 Vision Globale DSK/TMS320c5402 de TI

  8. 2-3 ARCHITECTURE D ’UNE CARTE µP • 2-3-1 Structure Générale/BUS µP ou DSP

  9. 2-3 ARCHITECTURE D ’UNE CARTE µP • 2-3-2 BUS de données (exemple sur 8 bits) • 0= 0v • 1= 5v (..) • tristate= rien • ou haute impédance

  10. 2-3-3 BUS d ’Adresses (exemple sur 3 bits)

  11. 2-3-4 Mapping MémoireOrganisation de la mémoire du TMS320C5510 0000h

  12. 2-4-3 Wait states

  13. 2-4-5 Temps pris par une instruction portw *(a), 0h p nombre de cycles d ’horloge pour waitstates mémoire programme d nombre de cycles d ’horloge pour waitstates mémoire données io nombre de cycles d ’horloge pour waitstates mémoire i/o

  14. Von Neuman Machine A STORED PROGRAM AND DATA ARITHMETIC LOGIC UNIT A = ADDRESS INPUT/ OUTPUT D D = DATA Harvard Architecture A A STORED DATA ARITHMETIC LOGIC UNIT STORED PROGRAM INPUT/ OUTPUT D D • 2-3-5 Architectures d’un Calculateur (source TI)

  15. 2-4 Voyage au centre du DSP 54x

  16. Data Read A/D Bus (C) Program A/D Bus (P) Data Read A/D Bus (D) MAC ALU DP @x2 AR0-7 Decode A B C54x Architecture PC XPC Addr Gen Data Write A/D Bus (E) MAC *AR2+, *AR3+, A ADD @x2, B ... 4

  17. 2-4-1 ALU/Registres et bus internes

  18. C5510 Architecture

  19. 2-4-2 Pipe-Line C5402

  20. Program A/D Bus (P) A Data Read A/D Bus (D) Ext’l Mem I/F Data Read A/D Bus (C) D Data Write A/D Bus (E) P F D A R X P F D A R X P F D A R X P F D A R X P F D A R X Full Pipeline C54x Pipeline Internal Memory External Memory • Internal: Up to 4 accesses / cycle • External: 1 access / cycle • up to 8M words program Pipeline Phases P F D A R X P - generate program address F - get opcode D - decode instruction A - generate read address R - read operands X - execute 6

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