Linux Operating System 許 富 皓

1. Linux Operating System 許 富 皓

2. Intel x86 Architecture

3. The Motherboard of a Computer

4. Evolution of Intel Microprocessors [Steve Gilhea]

5. An Intel Pentium 4 Processor

6. Install a Processor

7. Intel 64 [H. Wiklicky] Formerly known as EM64T or IA32e or x86-64 or x64 64-bit extended instruction set based on x86 processor architecture Originally by AMD Can also run 32-bit application on a 32-bit operating system Backward compatibility which is the key to the success of Intel x86 processor

8. IA-64 [H. Wiklicky] Itanium 2 processor Based on an entirely different architecture Only Intel Itanium processor employs this No backward compatibility with the IA-32 software Originally incorporated hardware emulation to the 32-bit application but now relying on software emulation

9. Intel 64 vs. IA-64 [H. Wiklicky] Two different instruction sets and architectures

10. 64-bit Intel Processors [wikipedia]

11. Intel x86 Registers

12. General Purpose Registers

13. Instruction Pointer

14. EFLAG Register

15. Segment Registers non-programmable part

16. Table Registers (System Address Registers)

17. Control Registers

18. Debug Registers

19. x86-64

20. X86-64[wikipedia] x86-64 (also known as x64, x86_64 and AMD64) is the 64-bit version of the x86 instruction set. The original specification was created by AMD, and has been implemented by AMD, Intel, and VIA.

21. Aliases of X86-64[wikipedia] Prior to launch, "x86-64" and "x86_64" were used to refer to the instruction set. Upon release, AMD named it AMD64. Intel initially used the names IA-32e and EM64T before finally settling on Intel 64 for their implementation. 

22. Compatibility Features of X86-64[wikipedia] x86-64 is fully backwards compatible with 16-bitand 32-bit x86 code. Because the full x86 16-bit and 32-bit instruction sets remain implemented in hardware without any intervening emulation, existing x86 executables run with no compatibility or performance penalties.

23. Intel x86-64 Registers

24. Traditional General Purpose Registers (1) [sandpile]

25. Traditional General Purpose Registers (2) [sandpile]

26. Traditional General Purpose Registers (3) [sandpile]

27. Traditional General Purpose Registers (4) [sandpile]

28. Instruction Pointer [sandpile]

29. rFLAGS [sandpile]

30. Control Registers (1) [sandpile]

31. Control Registers (2) [sandpile]

32. Segment Registers [sandpile]

33. IA 32 Real Mode vs. Protected Mode

34. Real Mode and Protected Mode • When an IA32 processor is powered up or reset, it is in real mode. • All modern IA32 operating systems use protected mode; however, when the computer boots, it starts up in real mode, so the part of the operating system responsible for switching into protected mode must operate in the real mode environment. • Instruction Set • 16-bit registers (real mode) vs. 16/32-bit registers (protected mode)

35. Addressing in Real Mode • segment register × 16+offset → physical address. • Using 16-bit offsets implicitly limits the CPU to 64k (=216) segment sizes. • No protection: program can load anything into segment register.

36. Addressing in Protected Mode selector:offset (logical address) Segmentation Unit linear address Paging Unit physical address

37. Interrupts in Real Mode • At the start of physical memory lies the real-mode Interrupt Vector Table (IVT). • The IVT contains 256 real-mode pointers for all of the real-mode Interrupt Service Routines (ISRs). • Real-mode pointers are 32-bits wide, formed by a 16-bit segment offset followed by a 16-bit segment address. The IVT has the following layout: 0 0x0000 [[offset][segment]] 1 0x0004 [[offset][segment]] 2 0x0008 [[offset][segment]] ... ... ... 255 0x03FC [[offset][segment]]

38. Interrupts in Protected Mode

39. How to Switch to Protected Mode • load GDTR with the pointer to the GDT-table. • disable interrupts ("cli") • load IDTR with the pointer to the IDT • set the PE-bit in the CR0 or MSW register. • make a far jump to the code to flush the PIQ. • Prefetch Input Queue (PIQ): pre-loading machine code from memory into this queue • initialize TR with the selector of a valid TSS. • optional: load LDTR with the pointer to the LDT-table.

40. Long Mode/IA-32e Mode [Intel]

41. IA-32e Mode (i.e. Long Mode) • In IA-32e mode, the processor supports two sub-modes: • compatibility mode and • 64-bit mode.

42. 64-bit Mode • 64-bit mode provides • 64-bit linear addressing and • support for physical address space larger than 64 GBytes.

43. Compatibility Mode Compatibility mode allows most legacy protected-mode applications to run unchanged.

44. Sub-Modes of IA-32e Mode [wikipedia]

45. Real Mode to Protected Mode The processor is placed in real-address mode following power-up or a reset. The PE flag in control register CR0 then controls whether the processor is operating in real-mode or protected mode.

46. IA32_EFER On systems that support IA-32e mode (i.e. long mode), the extended feature enable register (IA32_EFER) is available. This model specific register controls activation of IA-32e mode and other IA-32e mode operations.

47. Protected Mode to IA-32e Mode (1) • The LMA bit (IA32_EFER.LMA[bit 10]) determines whether the processor is operating in IA-32e mode. • When the LMA is inactivated, the processor will operate in the standard x86 mode and will be compatible to the OSes and application of 16 and 32 bits. [Zelenovsky et al.] • When running in IA-32e mode, • 64-bit or compatibility sub-mode operation is determined by CS.L bit of the code segment.

48. Protected Mode to IA-32e Mode (2) • The processor enters into IA-32e mode from protected mode by • enabling paging and • setting the LME bit (IA32_EFER.LME[bit 8]).

49. Transitions Among the Processor’s Operating Modes

50. Endian Order • Depending on which computing system you use, you will have to consider the byte order in which multi-byte numbers are stored, particularly when you are writing those numbers to a file. • The two orders are called Little Endian and Big Endian.