16.317: Microprocessor System Design I

1. 16.317: Microprocessor System Design I Instructor: Dr. Michael Geiger Spring 2012 Lecture 23: Virtual memory examples

2. Lecture outline • Announcements/reminders • HW 3 due today • Lab 2 due 3/28 • Exam 2: 1 week from Wednesday • Lecture outline • Review • Virtual memory basics • VM and 80386 segmentation • Paging • Page table entries • Virtual memory examples Microprocessors I: Lecture 23

3. Review • Virtual memory • Allows programmer to see more memory than system has • Allows program to function with variable amount of memory • Address undergoes translation from virtual address to physical address • Page table handles translation • Indexed by page #; provides physical frame # • Page table can have multiple levels to save space • TLB caches translations to save time • 80386 specifics • Virtual address: 46 bits • Upper 14 bits of selector + 32 bits of offset • Physical address: 32 bits • If just using segments, physical address = linear address • If using paging (4 KB pages), linear address used to index 2-level page table Microprocessors I: Lecture 23

4. Page table and TLB entries • Page table indexed by virtual page # • Entries contain information needed for translation • At a minimum, includes • Frame # • Valid or present bit: entry actually contains valid translation • May also include • Dirty bit: frame has been modified • Reference bit: frame has been accessed • Protection bits • Read/write: what action(s) are permitted • User/supervisor: normal vs. system-level application • TLB also needs page number—not directly indexed Microprocessors I: Lecture 23

5. TLB example • Given the TLB state shown in the handout, translate the given linear addresses to physical addresses • 00004123H • 00010FFFH • 1F005000H Microprocessors I: Lecture 23

6. Example solution • With 4 KB pages • Lowest 12 bits of address = offset • Upper 20 bits of address = page # • Compare page # against all TLB entries • If present and valid, replace page # with frame # • 00004123H • Page # = 00004  valid translation in 4th TLB line • Frame # = 10000  Physical addr = 10000123H • 00010FFFH • Page # = 00010  valid translation in 2nd TLB line • Frame # = 12345  Physical addr = 12345FFFH • 1F005000H • Page # = 1F005  no valid translation  no physical address Microprocessors I: Lecture 23

7. Page table example • Given the state of the page directory and page table shown in the handout, translate the following linear addresses to physical addresses • 00003FA2H • 00801116H Microprocessors I: Lecture 23

8. Example solution • With 4 KB pages • Lowest 12 bits of address = offset • With two-level table • Upper 10 bits of address = page directory index • Next 10 bits of address = 2nd level page table index • Page directory index chooses line in directory • Directory entry gives upper 20 bits of starting address for 2nd level table • 2nd level page table index chooses line in 2nd level table • PT entry gives frame # Microprocessors I: Lecture 23

9. Example solution (cont.) • 00003FA2H • 00003H = 0000 0000 0000 0000 00112 • Line 0 of page directory • Upper 20 bits of PT address = 01000  PT 0 • Line 3 of PT 0 • Frame # = 16317  Physical addr = 16317FA2H • 00801116H • 00801H = 0000 0000 1000 0000 00012 • Line 2 of page directory • Upper 20 bits of PT address = 02000  PT 1 • Line 1 of PT1 • Frame # = 3F000  Physical addr = 3F000116H Microprocessors I: Lecture 23

10. Next time • 80386 interfaces Microprocessors I: Lecture 23