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DDU2004 Status

DDU2004 Status. J. Gilmore EMU Meeting, OSU April 2004. DDU Functions. What does the DDU do? High-Bandwidth data concentration 15 DMB _ DAQ via DCC, capable of continuous 640 MB/sec rate Full error checking and status monitoring

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DDU2004 Status

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  1. DDU2004 Status J. Gilmore EMU Meeting, OSU April 2004

  2. DDU Functions • What does the DDU do? • High-Bandwidth data concentration • 15 DMB _ DAQ via DCC, capable of continuous 640 MB/sec rate • Full error checking and status monitoring • CRC check, word count, event number, overflow, link status • FMM communication path for EMU DAQ • PC data readout via Gigabit Ethernet (local DAQ path)

  3. Full error checking implemented • Interface to VME • PC readout via Gigabit Ethernet (90 MB/s data transfer) • DMB calibration pulses, regular and random timing • S-Link64 tested • Need to integrate w/ FMM and TTS Old DDU Prototype First 9U DDU Board. Produced and tested in 2002, used for beam tests at CERN in 2003. • Worked well in beam tests • Needs additional functionality for use at LHC • New Virtex2 FPGAs can provide more consistent timing • More logic at input stage can provide better stability in case of bit errors

  4. FPGA FPGA FPGA FPGA FIFO FIFO New DDU Design FMM/Slow Control BUSY READY L1 Throttle Data Errors Loss of Synch JTAG via VME MGT-HSC DCC/DAQ via Backplane Fiber links from 15 DMBs CCB/TTC via Backplane S-Link Transceivers Gigabit Ethernet To Local DAQ

  5. DDU2004 Prototype DMB Input FPGAs 2 XILINX Virtex2Pro-20 4 Input FIFOs 512 KB each GBE FIFO 1024 KB VME FPGA XILINX Virtex2-500 FMM output port SLINK Mezzanine board connector 15 Optical fiber inputs (just 1 for now) Gbit Ethernet Output To Local DAQ DDU Control FPGA XILINX Virtex2Pro-7

  6. DDU2004 Plan • Old DDU Design • 2 Virtex-E FPGAs, 16 FIFOs, 17 ball-grid arrays! • NO ball-grid problems out of ~4800 ball-grid solder joints • Improvements in DDU2004 Prototype • Faster FPGAs & FIFOs, better timing • 4 FPGAs, 5 FIFOs, 9 ball-grid arrays • ~3700 ball-grid solder joints • Better data-loss handling • Allows recovery from data loss without reset • Implement two-way fiber communication • DMB-DDU and also DDU-DMB for feedback/control • Less expensive than previous design • All FPGAs programmed, hardware and firmware testing continues…

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