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Digital Logic Review: Understanding Gates and Notations

Explore binary, hex, complements, 2's complement, basic gates, Verilog primitives, De Morgan's theorems, gate behavior, and logical rules in digital logic circuit design. Learn about XNOR, NAND, NOR gates, and logic fundamentals.

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Digital Logic Review: Understanding Gates and Notations

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  1. Digital Logic Review Discussion D8.7

  2. Positional Notation N = P4P3P2P1P0 = P4b4 + P3b3 + P2b2 + P1b1 + P0b0 Binary 101102 = 1 x 24 + 0 x 23 + 1 x 22 + 1 x 21 + 0 x 20 = 16 + 0 + 4 + 2 + 0 = 2210

  3. Positional Notation N = P4P3P2P1P0 = P4b4 + P3b3 + P2b2 + P1b1 + P0b0 Hex 3AF16 = 3 x 162 + A x 161 + F x 160 = 3 x 256 + 10 x 16 + 15 x 1 = 768 + 160 + 15 = 94310

  4. Binary Hex 0110 1010 1000 6 A 8 1111 0101 1100 F 5 C

  5. Complement remaining bits Copy all bits to first 1 2’s complement Finding 2’s Complement 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0

  6. Negative NumberTake 2’s Complement 7510 = 4B16 = 01001011 -7510 = B516 = 10110101 FF -4B B4 +1 B5

  7. Basic Gates • NOT Gate • AND Gate • OR Gate • XOR Gate • NAND Gate • NOR Gate • XNOR Gate

  8. Y X 0 1 1 0 Basic Gates Y = ~X not(Y,X) X Y NOT X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 Z = X & Y and(Z,X,Y) X AND Z Y X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 Z = X | Y or(Z,X,Y) X OR Z Y Any logic circuit can be created using only these three gates

  9. NOT Gate X ~X ~~X = X X ~X ~~X 0 1 0 1 0 1 Behavior: The output of a NOT gate is the inverse (one’s complement) of the input

  10. AND Gate Behavior: The output of an AND gate is HIGH only if all inputs are HIGH assign Z = X[1] & X[2] & ... & X[n]; assign Z = &X; and(Z,X[1],X[2],...,X[n]);

  11. OR Gate Behavior: The output of an OR gate is LOW only if all inputs are LOW assign Z = X[1] | X[2] | ... | X[n]; assign Z = |X; or(Z,X[1],X[2],...,X[n]);

  12. Exclusive-OR (XOR) Gate Behavior: The output of an XOR gate is HIGH only if the number of HIGH inputs is ODD assign Z = X[1] ^ X[2] ^ ... ^ X[n]; assign Z = ^X; xor(Z,X[1],X[2],...,X[n]);

  13. X Z Y 2-Input XOR Gate XOR X Y Z 0 0 0 0 1 1 1 0 1 1 1 0 Z = X ^ Y xor(Z,X,Y) Note: if Y = 0, Z = X if Y = 1, Z = ~X Therefore, an XOR gate can be used as a controlled inverter

  14. Exclusive-NOR Gate XNOR (NOT – XOR) Behavior: The output of an XNOR gate is HIGH only if the number of HIGH inputs is EVEN assign Z = ~(X[1] ^ X[2] ^ ... ^ X[n]); assign Z = ~^X; xnor(Z,X[1],X[2],...,X[n]);

  15. 2-Input XNOR Gate XNOR X Y Z 0 0 1 0 1 0 1 0 0 1 1 1 X Z Y Z = ~(X ^ Y) Z = X ~^ Y xnor(Z,X,Y) Note: Z = 1 if X = Y Therefore, an XNOR gate can be used as an equality detector

  16. NAND Gate (NOT-AND) Behavior: The output of an NAND gate is LOW only if all inputs are HIGH assign Z = ~(X[1] & X[2] & ... & X[n]); assign Z = ~&X; nand(Z,X[1],X[2],...,X[n]);

  17. NOR Gate (NOT – OR) Behavior: The output of an NOR gate is HIGH only if all inputs are LOW assign Z = ~(X[1] | X[2] | ... | X[n]); assign Z = ~|X; nor(Z,X[1],X[2],...,X[n]);

  18. Gates4.v module gates ( X ,Z, Y ); input [4:1] X ; wire [4:1] X ; output [6:1] Z ; wire [6:1] Z ; output [6:1] Y ; wire [6:1] Y ; and(Z[6],X[1],X[2],X[3],X[4]); nand(Z[5],X[1],X[2],X[3],X[4]); or(Z[4],X[1],X[2],X[3],X[4]); nor(Z[3],X[1],X[2],X[3],X[4]); xor(Z[2],X[1],X[2],X[3],X[4]); xnor(Z[1],X[1],X[2],X[3],X[4]); assign Y[6] = &X; assign Y[5] = ~&X; assign Y[4] = |X; assign Y[3] = ~|X; assign Y[2] = ^X; assign Y[1] = ~^X; endmodule Verilog gate level primitives Verilog reduction operators

  19. and(Z[6],X[1],... nand(Z[5],X[1], ... or(Z[4],X[1], ... nor(Z[3],X[1], ... xor(Z[2],X[1], ... xnor(Z[1],X[1], ... assign Y[6] = &X; assign Y[5] = ~&X; assign Y[4] = |X; assign Y[3] = ~|X; assign Y[2] = ^X; assign Y[1] = ~^X;

  20. NAND Gate X Z X Z = Y Y Z = ~(X & Y) Z = ~X | ~Y X Y W Z 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 X Y ~X ~Y Z 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 0

  21. De Morgan’s Theorem-1 ~(X & Y) = ~X | ~Y • NOT all variables • Change & to | and | to & • NOT the result

  22. NOR Gate X X Z Z Y Y Z = ~(X | Y) Z = ~X & ~Y X Y Z 0 0 1 0 1 0 1 0 0 1 1 0 X Y ~X ~Y Z 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0

  23. De Morgan’s Theorem-2 ~(X | Y) = ~X & ~Y • NOT all variables • Change & to | and | to & • NOT the result

  24. Sum of Products Design X Y minterms 0 0 m0 = ~X & ~Y 0 1 m1 = ~X & Y 1 0 m2 = X & ~Y 1 1 m3 = X & Y

  25. Sum of Products Design Design an XOR gate X Y Z 0 0 0 0 1 1 1 0 1 1 1 0 m1 = ~X & Y m2 = X & ~Y Z = m1 | m2 = (~X & Y) | (X & ~Y)

  26. Product of Sums Design X Y minterms maxterms 0 0 m0 = ~X & ~Y M0 = ~m0 = X | Y 0 1 m1 = ~X & Y M1 = ~m1 = X | ~Y 1 0 m2 = X & ~Y M2 = ~m2 = ~X | Y 1 1 m3 = X & Y M3 = ~m3 = ~X | ~Y

  27. Product of Sums Design Design an XOR gate X Y Z 0 0 0 0 1 1 1 0 1 1 1 0 M0 = X | Y M3 = ~X | ~Y Z = M0 & M3 = (X | Y) & (~X | ~Y)

  28. ~X & Y Venn Diagrams X Y

  29. ~X & Y X & Y Unity X Y (X & Y) | (~X & Y) = Y Dual: (X | Y) & (~X | Y) = Y

  30. X & Y Absorption-1 X Y Y | (X & Y) = Y Dual: Y & (X | Y) = Y

  31. ~X & Y Absorption-2 X Y X | (~X & Y) = X | Y Dual: X & (~X | Y) = X & Y

  32. Distributive Law - a X | (Y & Z) = (X | Y) & (X | Z)

  33. Distributive Law - b X & (Y | Z) = (X & Y) | (X & Z)

  34. Venn Diagrams and Minterms

  35. Venn Diagrams and Minterms XYZ + XYZ + XYZ = XZ + XY

  36. YZ 00 01 11 10 X 0 1 3 2 0 4 5 7 6 1 Three-variable K-Maps 1 1 1 1 F = m0 | m2 | m5 | m7 = S(0,2,5,7)

  37. YZ 00 01 11 10 X 0 1 Three-variable K-Maps 1 1 1 1 F = X & Z | ~X & ~Z

  38. YZ 00 01 11 10 X 0 1 Three-variable K-Maps 1 1 1 1 1 1 F = Y | ~Z

  39. YZ 00 01 11 10 WX 0 1 3 2 00 4 5 7 6 01 12 13 15 14 11 8 9 11 10 10 Four-variable K-Maps F(W,X,Y,Z) = S(2,4,5,6,7,9,13,14,15)

  40. Four-variable K-Maps YZ 00 01 11 10 WX 00 1 F = ~W & X | X & Y | ~W & Y & ~Z | W & ~Y & Z 01 1 1 1 1 11 1 1 1 10 1

  41. Four-variable K-Maps YZ 00 01 11 10 WX F = ~W & Z 00 1 1 1 1 | W & X & Y 01 1 1 | ~X & ~Z 11 1 1 10 1 1

  42. A 1-Bit Comparator The variable Gout is 1 if Gin = 1 or if Ein = 1 andx > y. The variable Eout is 1 if Ein = 1 andx = y. Gout = Gin | Ein & x & ~y Eout = Ein & ~x & ~y | Ein & x & y = Ein & (~x & ~y | x & y) = Ein & (x ~^ y)

  43. module comp4 ( x, y, gt, eq, lt ); input [3:0] x ; wire [3:0] x ; input [3:0] y ; wire [3:0] y ; output lt ; wire lt ; output gt ; wire gt ; output eq ; wire eq ; A 4-Bit Comparator x 1 1 0 1 y 1 0 1 1 0 1 1 1 lt 0 0 1 0

  44. Turning on an LED

  45. Turning on an LED This is what we use in Lab

  46. 7-Segment Display

  47. 7-Segment Display seg7dec D(3:0) AtoG(6:0) Truth table D a b c d e f g 8 1 1 1 1 1 1 1 9 1 1 1 1 0 1 1 A 1 1 1 0 1 1 1 b 0 0 1 1 1 1 1 C 1 0 0 1 1 1 0 d 0 1 1 1 1 0 1 E 1 0 0 1 1 1 1 F 1 0 0 0 1 1 1 D a b c d e f g 0 1 1 1 1 1 1 0 1 0 1 1 0 0 0 0 2 1 1 0 1 1 0 1 3 1 1 1 1 0 0 1 4 0 1 1 0 0 1 1 5 1 0 1 1 0 1 1 6 1 0 1 1 1 1 1 7 1 1 1 0 0 0 0

  48. a f b g e c d module hex7seg(D,AtoG); input [3:0] D; output [6:0] AtoG; reg [6:0] AtoG; always @(D) case(D) 0: AtoG = 7'b1111110; 1: AtoG = 7'b0110000; 2: AtoG = 7'b1101101; 3: AtoG = 7'b1111001; 4: AtoG = 7'b0110011; 5: AtoG = 7'b1011011; 6: AtoG = 7'b1011111; 7: AtoG = 7'b1110000; 8: AtoG = 7'b1111111; 9: AtoG = 7'b1111011; 'hA: AtoG = 7'b1110111; 'hb: AtoG = 7'b0011111; 'hC: AtoG = 7'b1001110; 'hd: AtoG = 7'b0111101; 'hE: AtoG = 7'b1001111; 'hF: AtoG = 7'b1000111; default: AtoG = 7'b1111110; // 0 endcase endmodule hex7seg.v Verilog

  49. SW7seg.v Verilog // Title : Toggle switches to 7-Segment Display // Author : R. E. Haskell module SW7seg(SW,LEDR,AtoG,AAtoGG); input [7:0] SW; output [7:0]LEDR; output [6:0] AtoG; output [6:0] AAtoGG; wire [6:0] AtoG; wire [6:0] AAtoGG; wire [7:0] LEDR; assign LEDR = SW; hex7seg d7L(.D(SW[7:4]),.AtoG(AAtoGG)); hex7seg d7R(.D(SW[3:0]),.AtoG(AtoG)); endmodule AAtoGG AtoG

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