Clock Timing and Skew: Real Devices

1. Clock Timing and Skew:Real Devices Note: material will include larger, slower devices. Smaller ones may be faster. Check data sheets.

2. Actel • Xilinx • Chip Express QYH500 • Atmel/Honeywell AT6K • MRC • UTMC/Quicklogic

3. Atmel/Honeywell AT6K

4. Atmel/Honeywell AT6K

5. QL4090

6. QL4090

7. Act 1

8. Act 2: 1280

9. Act 3

10. Act 3: Zoomed In

11. Act 3

12. Act 3A14100A, Worst-Case Commercial Conditions

13. Act 3 Act 3A14100A, Worst-Case Commercial Conditions Critical clock-to-clock skews.

14. RT54SX32 - 0.6 m

15. RT54SX32 - 0.6 m

16. RT54SX72S - 0.25 m Check your hold times! Note: 4.5V Vcci; also supports 3.0 V.

17. RT54SX72S - 0.25 m Check your hold times! Note: 4.5V Vcci; also supports 3.0 V.

18. SX-S Timing Note the clock load in each R-Cell is 3x in the SX-S series.

19. AX PLL Performance Note: Can not run with a moderate frequency clock.

20. Skew, Virtex, IOB Flip-Flops Skews increase with device size.

21. Virtex, CLK  Out, w/ DLL

22. Virtex, CLK  Out, w/out DLL

23. Virtex DLL Timing Parameters Notes 1. Like many FPGA parameters, guaranteed but not tested. 2. Can not run with a moderate frequency clock.

24. Virtex DLL Timing Parameters

25. Virtex DLL Timing Parameters Notes