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Semiconductor Device Modeling and Characterization – EE5342 Lecture 28 – Spring 2011. Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/. Ideal 2-terminal MOS capacitor/diode. conducting gate, area = LW. V gate. -x ox. SiO 2. 0. y. 0. L. silicon substrate. t sub.
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Semiconductor Device Modeling and Characterization – EE5342 Lecture 28 – Spring 2011 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/
Ideal 2-terminalMOS capacitor/diode conducting gate, area = LW Vgate -xox SiO2 0 y 0 L silicon substrate tsub Vsub x
Band models (approx. scale) metal silicon dioxide p-type s/c Eo Eo qcox ~ 0.95 eV Eo qcSi= 4.05eV qfm= 4.1 eV for Al Ec qfs,p Eg,ox ~ 8 eV Ec EFm EFi EFp Ev Ev
Flat band condition (approx. scale) Al SiO2 p-Si q(fm-cox)= 3.15 eV q(cox-cSi)=3.1eV Ec,Ox qffp= 3.95eV EFm Ec Eg,ox~8eV EFi EFp Ev Ev
Equivalent circuitfor Flat-Band • Surface effect analogous to the extr Debye length = LD,extr = [eVt/(qNa)]1/2 • Debye cap, C’D,extr = eSi/LD,extr • Oxide cap, C’Ox = eOx/xOx • Net C is the series comb C’Ox C’D,extr
Accumulation forVgate< VFB Vgate< VFB -xox SiO2 EOx,x<0 0 holes p-type Si tsub Vsub = 0 x
Accumulationp-Si, Vgs < VFB Fig 10.4a*
Equivalent circuitfor accumulation • Accum depth analogous to the accum Debye length = LD,acc = [eVt/(qps)]1/2 • Accum cap, C’acc = eSi/LD,acc • Oxide cap, C’Ox = eOx/xOx • Net C is the series comb C’Ox C’acc
Depletion for p-Si, Vgate> VFB Vgate> VFB -xox SiO2 EOx,x> 0 0 Depl Reg Acceptors p-type Si tsub Vsub = 0 x
Depletion forp-Si, Vgate> VFB Fig 10.4b*
Equivalent circuitfor depletion • Depl depth given by the usual formula = xdepl = [2eSi(Vbb)/(qNa)]1/2 • Depl cap, C’depl = eSi/xdepl • Oxide cap, C’Ox = eOx/xOx • Net C is the series comb C’Ox C’depl
Inversion for p-SiVgate>VTh>VFB Vgate> VFB EOx,x> 0 e- e- e- e- e- Acceptors Depl Reg Vsub = 0
Inversion for p-SiVgate>VTh>VFB Fig 10.5*
Approximation concept“Onset of Strong Inv” • OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG= VTh • Assume ns = 0 for VG< VTh • Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh • Cd,min = eSi/xd,max for VG > VTh • Assume ns > 0 for VG > VTh
MOS Bands at OSIp-substr = n-channel Fig 10.9*
Equivalent circuitabove OSI • Depl depth given by the maximum depl = xd,max = [2eSi|2fp|/(qNa)]1/2 • Depl cap, C’d,min = eSi/xd,max • Oxide cap, C’Ox = eOx/xOx • Net C is the series comb C’Ox C’d,min
n-substr accumulation (p-channel) Fig 10.7a*
n-substrate depletion(p-channel) Fig 10.7b*
n-substrate inversion(p-channel) Fig 10.7*
fms (V) Fig 10.15* NB (cm-3) Typical fms values
Flat band with oxidecharge (approx. scale) Al SiO2 p-Si +<--Vox-->- q(Vox) Ec,Ox q(ffp-cox) Ex q(fm-cox) Eg,ox~8eV Ec EFm EFi EFp q(VFB) Ev VFB= VG-VB, when Si bands are flat Ev
Inversion for p-SiVgate>VTh>VFB Vgate> VFB EOx,x> 0 e- e- e- e- e- Acceptors Depl Reg Vsub = 0
Approximation concept“Onset of Strong Inv” • OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG= VTh • Assume ns = 0 for VG< VTh • Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh • Cd,min = eSi/xd,max for VG > VTh • Assume ns > 0 for VG > VTh
Fig 10.9* qfp 2q|fp| xd,max MOS Bands at OSIp-substr = n-channel
Computing the D.R. W and Q at O.S.I. Ex Emax x
Fully biased n-MOScapacitor VG Channel if VG > VT VS VD EOx,x> 0 e- e- e- e- e- e- n+ n+ p-substrate Vsub=VB Depl Reg Acceptors y 0 L
MOS energy bands atSi surface for n-channel Fig 8.10**
Ex Emax x Computing the D.R. W and Q at O.S.I.
Q’d,max and xd,max forbiased MOS capacitor Fig 8.11** xd,max (mm)
n-channel VT forVC = VB = 0 Fig 10.20*
References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986