1 / 19

MPC 555: Queued Serial Module

MPC 555: Queued Serial Module. MPC 555 QSM. QSPI: Queued Serial Peripheral Interface: full duplex serial, synchronous interface. 160B of queue RAM. SCI1 & 2 : serial communication interfaces. QSM Block Diagram. QSM Configuration Register. QSM Interrupts. QSM Configuration Register.

brenna
Download Presentation

MPC 555: Queued Serial Module

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. MPC 555: Queued Serial Module

  2. MPC 555 QSM QSPI: Queued Serial Peripheral Interface: full duplex serial, synchronous interface. 160B of queue RAM. SCI1 & 2: serial communication interfaces

  3. QSM Block Diagram

  4. QSM Configuration Register

  5. QSM Interrupts

  6. QSM Configuration Register

  7. QSM Interrupt Registers

  8. Queued Serial Peripheral Interface

  9. QSPI • 2 wire half duplex or 3-wire full duplex. • Many baud rates, clocking, and interrupt options. • Transfer chunks (serial) 8-16 bits. • 160B RAM stores data (in and out), and commands/control words. • CPU can queue up to 32 serial transfers in one interaction. • A pointer points to the data to be transferred. Normally incremented after each transfer.

  10. QSPI contd. • QSPI has its own 4 chip-select pins. • The queued transfer commands can be run in a loop in wrap-around mode. • A standard delay of 17 IMB cycles (0.8µs) between two transfer commands (chunks of serial transfer).

  11. QSPI Programming 0000: 16 bits; 1000: 8 bits; 1001: 9 bits; ….; 1111: 15 bits

  12. QSPI Programming

  13. QSPI Programming • SPSR: QSPI Status register, a 8-bit subfield of SPCR3. • Many other sources of interrupt --- each with its own status and interrupt enable bit. • HALTA: Halt ack. • MODF: mode fault flag.

  14. QSPI RAM Only CPU can write Right justified

  15. RAM Commands Multiple peripheral CS can be asserted CONT: continue asserting CS after transfer completed.

  16. QSPI Overall operation QSPI RAM each entry: 1 word of transmit data, 1 word of receive data, 1B of command CPU writes the command queue of QSPI CPU writes transmit data and enables QSPI. QSPI completes the transfer, sets the completion flag SPIF SPE bit in SPCR1 to enable the QSPI. When done QSPI disables itself. If HALT in SPCR3 on, then QSPI halts after each serial transfer and sets HALTA.

  17. QSPI Interrupt sources • Three sources of interrupt (all on the same vector). • SPIF (finished). • MODF: Mode fault (inconsistent configuration). • HALTA: acknowledge HALT.

  18. QSM Initialization

  19. QSM Op

More Related