1 / 27

B. Cronquist 1 , R. Katz 2 , J.J. Wang 1 , J. McCollum 1 ,

Radiation-Hardened/High Reliability Programmable Logic Using Modified Commercial-off-the-Shelf RTSX32S. B. Cronquist 1 , R. Katz 2 , J.J. Wang 1 , J. McCollum 1 , I. Kleyner 3 , I. Brill 3 , W. Parker 1 ,and K. A. LaBel 2 1 Actel Corporation, Sunnyvale, CA94086

brent-morrison
Download Presentation

B. Cronquist 1 , R. Katz 2 , J.J. Wang 1 , J. McCollum 1 ,

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Radiation-Hardened/High Reliability Programmable Logic Using Modified Commercial-off-the-ShelfRTSX32S B. Cronquist1, R. Katz2, J.J. Wang1, J. McCollum1, I. Kleyner3, I. Brill3, W. Parker1,and K. A. LaBel2 1Actel Corporation, Sunnyvale, CA94086 2NASA Goddard Space Flight Center, Greenbelt, MD20771 3Orbital Sciences Corporation, Greenbelt, MD20771 Cronquist MAPLD2000 B2 Page 1

  2. Outline • Introduction • Motivation • Technology • Methodology • Results and Discussion • Summary • Future Work Cronquist MAPLD2000 B2 Page 2

  3. Introduction • Field Programmable Gate Arrays (FPGAs) are desirable • Shorten development times • Low cost per design (low development costs) • Can deliver moderate to high logic density • Antifuse FPGAs are very compelling • Rad-hard non-volatile switch • Secure -- reverse engineering improbable • Cost-effective opportunity to harden the flip-flops Cronquist MAPLD2000 B2 Page 3

  4. Motivation • Flip-Flop (FF) SEU rate forces some missions to adopt “soft TMR” method to achieve SEU spec. • This uses 3 FFs and some combinatorial logic to implement, adversely affecting the logic density. • Antifuse technology is the most cost effective switch technology to implement “hard TMR (Hardened Latch)” in the FF. • Only 1000’s of FF in a high density part, not millions of configuration switches that need hardening. • 0.25m metal-to-metal (M2M) process technology node permits an affordable high density part. Cronquist MAPLD2000 B2 Page 4

  5. SX Device Architecture Antifuse Switch Logic Module Cronquist MAPLD2000 B2 Page 5

  6. SX Antifuse Switch Metal 3 Metal-to-Metal Antifuse Metal 2 Via Metal 1 Contact Silicon Cronquist MAPLD2000 B2 Page 6

  7. RTSXS Family Heritage nameprocessfoundry database RTSX 0.6m MEC 0.6um SX 0.35m CSM shrink of RTSX db SXA 0.25/.22m MEC,UMC shrink+ “A”features RTSXS 0.25m MEC SXA db+TMR+cntl +5vCMOS I/O Cronquist MAPLD2000 B2 Page 7

  8. Technology Comparison Attribute Commercial Rad-Tolerant Product A54SXA RT54SXS Foundry UMC/Matsushita (MEC) MEC Fab Taiwan/Japan Japan I/Os Same-except S has 5vCMOS selectable inputs Functionality Same Programming Same Software Designer R1-2000 Speed std, -1, -2,-3,-4 std, -1 Technology 0.25mm (.25/.22) 0.25mm antifuse CMOS antifuse CMOS Poly/Metal 1P, 3 or 4M Starting Material non-epi (bulk) Oxidations Commercial Cronquist MAPLD2000 B2 Page 8

  9. Technology Cntd... Attribute Commercial Rad-Tolerant Low Voltage Gate tox 50Å High Voltage Gate tox 150Å Isolation Oxide Shallow Trench Gate Poly Ti Salicide Planarization CMP oxide Intermetal Dielectric CMP oxide Contact Metallization Wplug Via Wplug Wiring TiTiN--Al/0.5%Cu-TiN Passivation PECVDSi3N4 + Polyimide Cnt/via step coverage 100% Programming time approx 20min Cronquist MAPLD2000 B2 Page 9

  10. 0.25m M2M Technology Reliability • Channel Hot Carriers • Low Voltage - 20yr @ 2.75Vcc, max f • High Voltage - 20yr @ 5.5v (I/O), max f • Gate Oxide TDDB - < 0.2% in 20yrs at 100 °C, max Vcc • M2M Fuse Link Resistance - 25ohms typical after prog & soak • Lifetest - HTOL, LTOL(-55 °C) • ESD Class II (2-4 kV) HBM Cronquist MAPLD2000 B2 Page 10

  11. R-Cell Functional Primitive RTSX-S R-Cell is functionally equivalent to all Actel SX family members. RTSX-S RTSX, A54SX, A54SXA PSETB PSETB • D FF with enable • Choice of Preset, Clear or Neither • No special libraries required for the RTSX-S SEU hardened FF. D Q D Q = E E CLK CLK CLRB CLRB Cronquist MAPLD2000 B2 Page 11

  12. R-cell Implementation RTSX-S FFs - designed so that upsets cannot accumulate and cause errors in the absence of a clock pulse. Q D CLKB CLK • Standard D FF consists of a master and a slave latch, either of which can be flipped when bombarded by a heavy ion. Cronquist MAPLD2000 B2 Page 12

  13. R-cell Implementation (cont’d) D Q Voter Gate CLKB CLK • RTSX-S D FF consists of 3 master and 3 slave latches • Feedback path of each latch is voted with the output of the other two latches. • Voting the feedback path prevents any latches from changing state due to a single upset. • Upsets are asynchronously reset, and not integrated in the absence of a clock pulse. Cronquist MAPLD2000 B2 Page 13

  14. R-cell Testing Special test circuitry enables independent testing of the three latches comprising the R-Cell slave or master. D • Circuitry can only be accessed on an un-programmed die. • FF is tested at final test and after burn-in Tst1 Voter Gate Tst2 Tst3 CLKB Test Circuitry Cronquist MAPLD2000 B2 Page 14

  15. I/O Features Description Function Input buffer • 4 level selections - LVTTL, 3.3V PCI, 5V CMOS, 5V PCI/TTL • Selectable on an individual I/O basis • 5 volt tolerant • “Hot-swap” capability • Unpowered dev. I/O doesn’t sink current • Can be used for “cold-sparing” • Selectable on an individual I/O basis • Individually selectable low-slew option • Indiv. selectable current lamp preventing reflections of a signal > 3.3 volts (VCCI) • Indiv. selectable pull-ups/downs during power-up (default to power-up in tri-state) • Enables deterministic power-up of device • Pull-ups/downs are disabled 50ns after VCCA (array) is powered up and functioning • VCCA & VCCI can be powered in any order Output buffer 3.3 Volt PCI Power-up Cronquist MAPLD2000 B2 Page 15

  16. RTSX-S Input Levels Input levels independently selectable on an I/O by I/O basis. VCCI=5.0V VCCI=3.3V Vih(min) Vil(max) • Trip points referenced to VCCI which controls the output drive level. • 5.0V CMOS selection designed exclusively for RTSXS to maximize noise immunity in a 5 volt CMOS system. Cronquist MAPLD2000 B2 Page 16

  17. Cold Sparing • “Hot-Swap” selectable on an individual I/O basis. • Spare boards can be powered off until needed. • Low TID component boards can be powered off in order to extend mission lifetime. Powered-up Board 3.3/5 Volts Powered-down Board VCCI RTSX-S 0 Volts GND Active Bus or Backplane VCCI RTSX-S GND I/O w/ ” Hot-Swap” Enabled does not sink current Cronquist MAPLD2000 B2 Page 17

  18. Deterministic Power-up (outputs can be set to power-up either high or low) VCCA VCCI • Pull-ups /downs are selectable on an individual I/O basis • Pull-up follows VCCI • Pull-downs and pull-ups are dis- abled 50 ns after VCCA reaches 2.5V and therefore do not draw current during regular operation. • Once VCCA is powered-up, 50ns is required for a valid signal to propagate to the outputs before the pull-ups /downs are disabled RTSX-S Pull-up enabled PRE Input Driven low or external POR Signal CLR Pull-down enabled Cronquist MAPLD2000 B2 Page 18

  19. Methodology • Wafer sort and Package Final Test • The normal 100% test coverage with a modified logic modules test to reflect the hard TMR circuitry checks. • Total Dose (NASA Goddard Co60 cell) • Functional failure: in-situ monitor of functionality and IDDSTANDBY • Parametric failure: Mil std TM1019.5, room temp biased anneal for space applications Cronquist MAPLD2000 B2 Page 19

  20. Methodology (pg2) • SEE (SEL, SEU, SEDR) • NASA shift register design with up to 800 FFs, continuous monitor of IDD and functionality, time stamping errors--digital ‘strip charts’ recorded. Details: see http:/rk.gsfc.nasa.gov/richcontent/fpga_content/SEU_Hardening/Test_BNL0900.htm and Test_BNL0800.htm • Brookhaven National Labs • Room temp, nominal 1MHz clock (500 Hz to 5 MHz), VCC=2.5v • Nominal 10 million p/cm2 fluence • Multiple tilts and rolls -- test redundant structures • Calibrated with previously tested RTSX32A part: FF error count within 1% of previous tests. Cronquist MAPLD2000 B2 Page 20

  21. DUT CARD Cronquist MAPLD2000 B2 Page 21

  22. DUT CARD CLOSEUP Cronquist MAPLD2000 B2 Page 22

  23. Cronquist MAPLD2000 B2 Page 23

  24. Heavy Ion SEU Test Results FF only Cronquist MAPLD2000 B2 Page 24

  25. SEE Test Results • Haredened FF SEU: Statistically non-measurable (no upsets at nominal Vcc). GEO 100milAl/solar-min gives 1.4E-15 u/b-d upset rate. • SEL: Prototype RT54SX32S at BNL with LET up to 74MeV-cm2/mg at Vcc=2.5v. No latchup. • SEDR: Prototype RT54SX32S at BNL with LET up to 74MeV-cm2/mg (Iodine at 0 deg tilt) at Vcc=2.5v. No rupture. A54SX32A (with same antifuse) no rupture at Vcc=3.0v • No clock upset has been detected on the regular clock. HCLK still to be tested. Cronquist MAPLD2000 B2 Page 25

  26. Summary • Prototype RTSX32S delivers very good results • TID of 65k rad(Si) functional • No SEL or SEDR (up to 74MeV-cm2/mg. Tested) • Practically immune FF cell • Demonstrated that modification of a dense commercial design can achieve SEU hard performance levels. Cronquist MAPLD2000 B2 Page 26

  27. Future Work • TID and SEE characterization of production units • Prompt Dose characterization • Attempt to quantify ultra-shallow angle upset probability • Continue the search for SET • Produce and characterize additional SX-S family members. Cronquist MAPLD2000 B2 Page 27

More Related