User-Defined Primitives

1. User-Defined Primitives Lecture 7 ELEN 468

2. Primitives • Predefined primitives • Total 26 predefined primitives • All combinational • Tri-state primitives have multiple outputs, others have single output • User-defined primitives • Table-like description • Combinational or sequential • Single output • Different from modules • Used to model cell library • More efficient ELEN 468

3. 2-bit multiplexer select primitive mux_prim (mux_out, select, a, b); output mux_out; input select, a, b; table // select a b : mux_out 0 0 0 : 0; // Table order = port order 0 0 1 : 0; // One output, multiple inputs, no inout 0 0 x : 0; // Only 0, 1, x on input and output 0 1 0 : 1; // A z input in simulation is treated as x 0 1 1 : 1; // Last column is the output 0 1 x : 1; // select a b : mux_out 1 0 0 : 0; 1 1 0 : 0; 1 x 0 : 0; 1 0 1 : 1; 1 1 1 : 1; 1 x 1 : 1; x 0 0 : 0; // Reduces pessimism x 1 1 : 1; endtable // Combinations not specified will produce output “x” endprimitive a mux_out mux_prim b ELEN 468

4. Primitive Notations • 0, 1, x • ? : {0, 1, x} • b : {0, 1} ELEN 468

5. Shorthand Notation table // select a b : mux_out 0 0 ? : 0; 0 1 ? : 1; 1 ? 0 : 0; 1 ? 1 : 1; ? 0 0 : 0; ? 1 1 : 1; endtable ELEN 468

6. Verilog Primitives • Instantiated in the same manner as predefined primitives. • The output port must be type net in a combinational primitive, and type reg in a sequential primitive • No inout • Anything unspecified is treated as X) ELEN 468

7. Sequential Primitives • n inputs • 1 state and 1 output • n+2 columns • inputs, state, output/next state • Two types: • Level sensitive • Edge sensitive ELEN 468

8. Level Sensitive Latch enable primitive latch (q_out, enable, data); output q_out; input enable, data; reg q_out; table // en data : state : q_out/next state 1 1 : ? : 1; 1 0 : ? : 0; 0 ? : ? : –; endtable endprimitive q_out data Transparent Latch ELEN 468

9. Edge-Sensitive Latch primitive d_prim1 (q_out, clock, data); output q_out; input clock, data; reg q_out; table // clk data : state : q_out/next state (01) 0 : ? : 0; // Rising clock edge (01) 1 : ? : 1; (0?) 1 : 1 : 1; (?0) ? : ? : -; // Falling clock edge ? (??) : ? : -; // Steady clock endprimitive q_out data d_flop clock ELEN 468

10. More Primitive Notations • - : no change (output/next state) • (vw) : v{0, 1, x} -> w{0, 1, x} • * : {0, 1, x} -> {0, 1, x} • r : (01) • f : (10) • p : (01), (0x), (x1), (0z), (z1) • n : (10), (1x), (x0), (1z), (z0) ELEN 468

11. Shorthand Notation // edge sensitive latch table // clk data : state: q_out/next state r 0 : ? : 0; // Rising clock edge r 1 : ? : 1; p 1 : 1: 1; n ? : ? : -; // Falling clock edge ? * : ? : -; // Steady clock endprimitive ELEN 468

12. Exercise • What is the difference between “?” and “*” ? • What is the meaning of “(?,?)”? • What is the difference between “r” and “p”, between “f” and “n”? • What is the difference between “x” and “-”? • What symbol(s) can be used at output/next state? • What is the difference between “?”, “x”, and “b”? ELEN 468

13. Level-S Dominates Edge-S preset j k q_out clk clear ELEN 468

14. State Initialization • “Initial” only initializes in simulation • Define your own “preset” to initialize primitive d_prim2 (q_out, clock, data); output q_out; input clock, data; reg q_out; initial q_out = 0; table … endtable endprimitive ELEN 468

15. Summary • Each row specify a transition on only one input • All no-effect transitions should be stated or the results will be X • Only 0,1,x,- are allowed for outputs • Input Z is treated as X • Input order is the specification order ELEN 468

16. Correct Error primitive Half_Adder ( sum, c_out, b, a); output sum, c_out; input a, b; table a b : sum : c_out 0 0 : 0 : 0; 0 1 : 1 : 1; ? 0 : a : 0; 1 1 : 0 : 1; x x : x : x; endtable endprimitive ELEN 468

17. Corrected primitive Half_Adder_Sum (sum, a, b); output sum; input a, b; table // a b : sum 0 0 : 0 ; 0 1 : 1 ; 1 0 : 1 ; 1 1 : 0 ; endtable endprimitive ELEN 468

18. Example Module d_flop(clock, data, q, q_bar); input clock, data; output q, q_bar; wire q_out; d_prim1(q_out, clock, data); buf (q, q_out); not (q_bar, q_out); endmodule ELEN 468