Presenter : Cheng-Ta Wu

1. National Sun Yat-sen University Embedded System LaboratoryCorrect-by-Construction Multi-Component SoC Design Presenter : Cheng-Ta Wu RoopakSinha , POP ART Team INRIA Rhone Alpes France Partha S Roop, ZoranSalcic Electrical and Computer Engineering University of Auckland Auckland, New Zealand SamikBasu Department of Computer Science Iowa State University Ames, IA Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012

2. Abstract Systems-on-chip (SoCs) contain multiple interconnected and interacting components. In this paper, we present a compositional approach for the integration of multiple components with a wide range of protocol mismatches into a single SoC. We show how SoC construction can be done in single-step when all components are integrated at once or it can also be performed incrementally by adding components to an already integrated design. Using a number of AMBA IPs, we show that the proposed framework is able to perform protocol conversion in many cases where existing approaches fail.

3. What’s the Problem • Manual integration IPs into SoC is a time consuming and error prone process . • Existing compositional techniques can check whether two or more IPs are compatible, but cannot enforce compatibility. • Existing approaches cannot address data-width mismatches, nor clock mismatches. In addition, no existing protocol conversion approach can generate converters to ensure the satisfaction of multiple constraints(specifications) on the behavior of the SoC.

4. Related works [8] Multi-clock SoC design using protocol conversion [9] Automated techniques for formal verification of SoCs Using the SKS (synchronous Kripke Structures) algorithm Extend This Paper

5. Proposed Method • This paper presents protocol conversion framework • It can addresses clock, data-width and control signal mismatches, and can integrate more than 2 protocols at once, making it more general than existing protocol conversion techniques.

6. Example : set-top receiver box SoC block diagram

7. The inputs of conversion process : Protocol • Each protocol is oversampled to describe its behavior with respect to the fastest clock in the SoC(mclk) • Address clock mismatch

8. The inputs of conversion process : CTL property, Classification of I/O • CTL properties • Control constraints • E.g., the set-top system remains receptive to reading the data from the remote control, the video decoder must never be disabled before a control unit check. • Data constraints • Data counter that are used to keep track of the data communication between IPs. • Address data-width mismatch • Classification of I/O • Shared signals • Signals are emitted and read by the IPs, such as “start” signal. • Environment(uncontrollable signals) • Inputs are read from (or outputs emitted to) the environment, such as “keyok” signal. • Converter(Missing control signals) • Protocol inputs are generated neither by the environment nor within the protocols, such as “ready” signal. • Address control signal mismatch

9. Different type signals processing of a converter • Environment (uncontrollable) signals • Shared signals • Converter (missing) signals

10. Approaches to SoC design

11. Experimental results • Data-width: • Case 1 : the same ; Case 2 : multiple ; Case 3&4 : unrelated, …

12. Conclusions • This paper propose a method to generate a converter and address the mismatches of clock, data-width, control signals of different IPs. • The flexible algorithm allows single-step or incremental design of SoCs.