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MTF7 status

MTF7 status. Alex Madorsky for UF group. Firmware Status. Firmware: Control to Core FPGA link working ~Compatible with AXI4 standard Throttling not supported Performance matches PCIe performance ~4 times better than standard Xilinx Chip2Chip link

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MTF7 status

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  1. MTF7 status Alex Madorsky for UF group

  2. Firmware Status • Firmware: • Control to Core FPGA link working • ~Compatible with AXI4 standard • Throttling not supported • Performance matches PCIe performance • ~4 times better than standard Xilinx Chip2Chip link • Data rate on user interface: 125 M x 64 bits (each direction) • Data rate on I/O pins: 625 M x 14 pins (each direction) • Serialization factor: 5 • Now working on adapting the TF computational core for Virtex-7

  3. Engineering manpower • We are hiring one PhD student from Engineering department for the summer • He will be working on firmware modules • Talking with another PhD student, so may have two extra engineers for the summer

  4. PT LUT module • Design finished • Price quotes received • Parts order formed • No funds available, project suspended…

  5. Progress in CERN • MP7 team is still busy with other tests • May have time this week for tests with MTF7 • Darin brought extra MTP cables to CERN for this purpose • PCIe MTP cables for production system are in CERN (also brought by Darin) • Petr’s team may have time to install them soon. • We have extra Vadatech crate and MCH here in UF • Waiting for PCIe adapter to arrive this week • Will ship the entire kit to CERN as soon as the adapter is received.

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