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Development done on Device Bonder to Address 3D Requirements in a Production Environment

Development done on Device Bonder to Address 3D Requirements in a Production Environment. Pascal Metzger , Joseph Macheda : SET Michael D. Stead, Keith A. Cooper : SETNA 131 impasse Barteudet , Saint-Jeoire, Haute-Savoie, France. Presentation Outline. Introduction : Why 3D ?

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Development done on Device Bonder to Address 3D Requirements in a Production Environment

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  1. Development done on Device Bonder to Address 3D Requirements in a Production Environment • Pascal Metzger, Joseph Macheda : SET • Michael D. Stead, Keith A. Cooper : SETNA • 131 impasse Barteudet, Saint-Jeoire, Haute-Savoie, France

  2. Presentation Outline • Introduction : Why 3D ? • Some recalls on processes • Consequences on Design of equipment • Summary

  3. 3D Stacking • 3D Stacking permits to integrate more functions in reduced space

  4. 3D Assets • Reduced path between layers / functions • Reduced R, C and L • Lower electrical consumption • Longer autonomy • Higher bandwidth • Less sensitive to electromagnetic interferences • Reduced utilization of noble materials

  5. 3D Assets • Reduced volume • Reduced size, thickness and weight of devices • Less fragile • Better ergonomics

  6. 3D Challenges • Heat management inside IC • Precision • Cycle time

  7. Presentation Outline • Introduction : Why 3D ? • Some recalls on processes • Consequences on Design of equipment • Summary

  8. Explored Processes • Aluminum microtubes • Room temperature process • 106 connections at a 10 μm pitch Source CEA-LETI

  9. Explored Processes • Molecular attachment • Room temperature process • Direct Cu-Cu bonding • High cleanliness requirements Source CEA-LETI

  10. Explored Processes • Hybrid collective bonding • Thermocompression Cu-Cu bonding Source College of Nanoscale Science and Engineering

  11. Explored Processes • Solder composition • Thermal tacking and single re-flow step Source Institute of Microelectronics, A*STAR

  12. Presentation Outline • Introduction : Why 3D ? • Some recalls on processes • Consequences on Design of equipment • Summary

  13. Consequenceson design of equipment • For R&D, the same equipment can drive several different processes • For production, especially HVM, specialization may not be avoided to optimize the cycle time

  14. Top reticule Microscope Bottom reticule Qualification method • Architecture

  15. Qualification method • Test vehicles = Quartz chip with verniers Both (Mixed) Chip (Top) Substrate (Bottom)

  16. Top reticule Microscope Bottom reticule Qualification method • Cycle • Pick up • Alignment • Contact • Bonding • Post Bond measurement • Repeat

  17. Thermal influence • Cycle at 21°C  ± 0.4 µm

  18. Thermal influence • Cycle at 200°C  ± 0.6 µm

  19. Thermal influence • Cycle at 200°C (perturbation)  ± 1 µm

  20. Thermal influence • No thermal gradient within a plate

  21. Thermal influence • Thermal gradient within a plate

  22. Thermal influence • Thermal gradient within a plate

  23. Thermal influence • Mismatch between CTE • Example Ø 100 mm wafers of SiO2 and Si µm °C

  24. Presentation Outline • Introduction : Why 3D ? • Some recalls on processes • Consequences on Design of equipment • Summary

  25. Summary • Several parameters, especially temperature, play a key role in final precision of assembly. • For HVM environment, cycle time is one of the most important parameter. • For 3D applications in HVM requiring high precision, the process will influence both precision and cycle time.

  26. Summary • The design of the equipment, choice of materials, control of environment will be influenced by process. • Trade off in versatility, cost and stability may be necessary. • What will be the precision, the throughput, the process which will be used ? These are crucial questions. • Thanks to SET team

  27. THANK YOU FOR YOUR KIND ATTENTION www.set-sas.fr

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