Low-Power Design of Electronic Circuits

1. ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsDynamic Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC5970-001/6970-001 Lecture 6

2. CMOS Dynamic Power Dynamic Power = Σ 0.5 αifclk CLiVDD2 All gates i ≈ 0.5 αfclk CLVDD2 ≈ α01fclk CLVDD2 where α average gate activity factor α01 = 0.5α, average 0→1 trans. fclk clock frequency CL total load capacitance VDD supply voltage ELEC5970-001/6970-001 Lecture 6

3. Example: 0.25μm CMOS Chip • f = 500MHz • Average capacitance = 15fF/gate • VDD = 2.5V • 106 gates • Power = α01f CLVDD2 = α01×500×106×(15×10-15×106) ×2.52 = 46.9W, for α01 = 1.0 ELEC5970-001/6970-001 Lecture 6

4. Signal Activity, α T=1/f Clock α01= 1.0 α01= 0.5 Comb. signals α01= 0.5 ELEC5970-001/6970-001 Lecture 6

5. Reducing Dynamic Power • Dynamic power reduction is • Quadratic with reduction of supply voltage • Linear with reduction of capacitance ELEC5970-001/6970-001 Lecture 6

6. 0.25μm CMOS Inverter, VDD=2.5V 2.5 2.0 1.5 1.0 0.5 0 0 -4 -8 -12 -16 -20 Gain Vout(V) 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 Vin (V) Vin (V) ELEC5970-001/6970-001 Lecture 6

7. 0.25μm CMOS Inverter, VDD< 2.5V 2.5 2.0 1.5 1.0 0.5 0 0.2 0.15 0.1 0.05 0 Vout (V) Vout(V) 0 0.5 1.0 1.5 2.0 2.5 0 0.05 0.1 0.15 0.2 Gain = -1 Vin (V) Vin (V) ELEC5970-001/6970-001 Lecture 6

8. Lower Bound on VDD • For proper operation of gate, maximum gain (for Vin = VDD/2) should be greater than 1. • Gainmax = -(1/n)[exp(VDD /2ΦT) – 1] = -1 • n = 1.5 • ΦT = kT/q = 26mV • VDD = 48V • VDDmin > 2 to 4 times kT/q or ~100mV at room temperature (27oC) • Ref.: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003. ELEC5970-001/6970-001 Lecture 6

9. Impact of VDD on Performance CLVDD Inverter delay = K ─────── (VDD – Vt )α 40 30 20 10 0 Delay (ns) Power Delay 0.6V 1.8V 3.0V VDD VDD=Vt ELEC5970-001/6970-001 Lecture 6

10. Optimum Power × Delay VDD3 Power × Delay, PD = constant × ─────── (VDD – Vt)α For minimum power-delay product, d(PD)/dVDD = 0 3Vt VDD = ─── 3 – α For long channel devices, α = 2, VDD = 3Vt For very short channel devices, α = 1, VDD = 1.5Vt ELEC5970-001/6970-001 Lecture 6

11. Transistor Sizing for Performance • Problem: If we increase W/L to make the charging or discharging of load capacitance, then the increased W increases the load for the driving gate Cin CL ELEC5970-001/6970-001 Lecture 6

12. Fixed-Taper Buffer Delay = t0 αn-1 αi-1 α2 α 1 Vout Vin Cin CL Ci= αi-1Cin CL = αnCin Ref.: J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, Piscataway, New Jersey: IEEE Press, 2004. ELEC5970-001/6970-001 Lecture 6

13. Buffer (Cont.) αn= CL/Cin ln (CL/Cin) n = ────── ln α ith stage delay, ti = αt0, i = 1, . . . n, because each stage drives a stage α times bigger than itself. ELEC5970-001/6970-001 Lecture 6

14. Buffer (Cont.) n Total delay = Σti = nαt0 i=1 = ln(CL/Cin) αt0/ln(α) ELEC5970-001/6970-001 Lecture 6

15. Buffer (Cont.) Differentiating total delay with respect to α and equating to 0, we get αopt = e ≈ 2.7 The optimum number of stages is nopt = ln(CL/Cin) ELEC5970-001/6970-001 Lecture 6

16. Further Reading B. S. Cherkauer and E. G. Friedman, “A Unified Design Methodology for CMOS Tapered Buffers,” IEEE Trans. VLSI Systems, vol. 3, no. 1, pp. 99-111, March 1995. ELEC5970-001/6970-001 Lecture 6